## Interface Electronics## Laboratory 03: ADC DAC analysis instructions## Group M## ***640, R |

- ADC DAC schematic
- FFT Simulation
- Ramp test
- Further analysis
- INL and DNL analysis
- ADC histogram test
- Sine output analysis
- ADC histogram test on sine wave form
- FFT Javascript tool
- R2R DAC analysis
- Altering the R2R DAC
- Tests on new circuit(signal output)
- Tests on new circuit(ramp output)
- Extracting data through LTSPICE

The AC block shall convert an analoge sine signal into digital which the DAC converts into analoge, as shown by simulation in the graphic next to the circuit.

A window appears to choose the number of values for the FFT. We set it to 65536.

Finally a graphical representation of the SNR is obtained.

This input must have its parameters as specified by the directive "V1 in1 0 PULSE", with 665.36us for rise and fall time, which corresponds to the simulation time.

The simulation gives as result an equally distribuited step graph along the ramp.

Through a Javascript program in the personal page of Prof. Vollrath we can upload the .RAW file in order to obtain curves of the converters.

Here is necessary to state start and stop time. These must be the indicated by the transient directive.

For the time step we divide the simulation time by the number of steps in the last resulting curve, which were 16.

For that, the desired range is introduced in the indicated box. In our case we want 0-15.

We click then on map to integer to get the graph.

Now we click on "DAC INL, DNL analysis" button to see results.

As expected, there is no error in any of the intervals.

Doing this causes errors as shown below.

Because of the time step, it is taken 8 samples for each iteration of the mapping range, making the scaled curve look like a step.

For the INL and DNL there is no error.

To do so, the original sine voltage source must be enabled again and disabled the pulse source.

A simulation is run in order to get the needed data into the .RAW file.

The tool takes 128 samples throughout the period, making up 16 values from top to bottom of the sine wave.

The sine output is then scaled into the specified range.

For this case, by copying the values table that is calculated with the tool "Map to integer" it is possible to solve this issue by using another tool by following the link of FFT data processing as indicated at the end of the scaled values table.

First, the copied values must be pasted in the "Input data" box. The "number of bit" box value has to contain 4, which correspond to our the number bits of the converters.

Clicking on the "Read positive integer data" and "Generate Charts" buttons processes the given data.

Aditionally, a true INL and DNL is obtained and a Signal to Noise table is computed as shown below.

This replaces the first DAC.

Running a simulation shows the same behavior just like the last one.

Important ot see is the INL DNL histogram as it shows clearly errors

Utilizing the RAW data and setting a time step of 40.96us on the Javascript tool yields the next results.

The new DAC makes their most pronounced erros arround the middle of the simulation as can be seen.

Following a syntax format as indicated below we decide to measure the output at the time of 81.92us

Once the simulation is complete, the captured value can be located on the GNU tab View/SPICE Error Log.

Hochschule für angewandte Wissenschaften Kempten, Jörg Vollrath, Bahnhofstraße 61 · 87435 Kempten

Tel. 0831/25 23-0 · Fax 0831/25 23-104 · E-Mail: joerg.vollrath(at)fh-kempten.de

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