Hochschule Kempten      
Fakult├Ąt Elektrotechnik      
Interface Electronics       Fachgebiet Elektronik, Prof. Vollrath      

Interface Electronics

Laboratory 01

ADC & DAC LTspice Simulation

GroupB2, ****84, I



Overview

Installation of Webpage

Test for 4 Bit ADC and DAC

A 4 Bit ADC and DAC test can be simulated in LTSPICE.
The files were download and LTspice simulation was started
The output file size can be limited by using the .save dialog option.

The voltage source was added with aramp form 0V to 1V with a rise time of 655µs.
16 steps can be seen. With a mesaurement statement, the voltage levels were:

.Measure TRAN V0000 FIND V(Vout) AT=20u

At 60us time the output voltageb of 0.0625V is given for the code 0001.
V0001: V(Vout)=0.0625 at 6e-005

No error in the voltage level can be seen. It is an Ideal ADC and DAC.

LTSPICE schematics of DAC_3Bit

JavaScript module
SPICE_HTML_2018_02/LTSPICE.js

Canvas, Control, Link, Code parts

Add schematics to processing list

ID has to be the same as the schematic name.

LTSPICE DAC_3Bit Output


With a mesaurement statement, the voltage levels were:

.Measure TRAN V0000 FIND V(Vout) AT=0.95u

At 1.95us time the output voltageb of 1.95µV is given for the code 0001.
V0001: V(Vout)=0.399999V at 1.95e-006

As you see in schematic there is transistor switches so when the input voltages change then because of changing the transection on/off
of the transistor its generte a spike at the output voltage.

DNL & INL Calculation


Summary

  • The main think that that I have learned in this lab is to design Webpage Report.
  • I test or check the behaviour of 4-Bit ADC & DAC with ramp voltage of 0v to 1v.
  • I analysis that at this ramp voltages the 4-Bit ADC & DAC act as Ideal because no error seen at the Voltage level.
  • I also analysis the DAC_3Bit and get output curve which shows its behaviovr.
  • In DAC_3Bit there is a spike its generate because of On/Off transection of transistor when Input voltges change.

References


[1] Making of a Webreport , Vollrath