# Overview

• Simulation and analysis of a Ramp Signal: DNL, INL, LSB
• Simulation and analysis of a Sine Signal: FFT, DNL, INL, SNR
• This is a laboratory to simulate an ADC DAC set up with Ramp and Sine test
• Summary

# ADC DAC Schematic & Simulation for Sine

 I uesd Ideal ADC and DAC component to make a circuit of 4-Bit ADC & DAC I check the behaviour of my circuit It shows a Sine wave with 11 periods as shown in figure # FFT Behaviour of 4-Bit ADC DAC for Sine

 After check the sine waveform I find the FFT behaviour of this sine signal. I check the Signal to Noise of input and output of the FFT Signal. As you see in graph the input signal has less noise as compare to Output because of 4-Bit Input. Output is very noisy and its very difficult to find the noise flow as well as values of Harmonics. LTspice didnot provide all values for data converter Analysis so thats why we use external Data Processing. # ADC DAC Schematic & Simulation for Ramp

 Ramp test I used another voltage source text with same rise and fall time 655.36u. pulse voltage source:V1 in1 0 PULSE(0 1 0 655.36u 655.36u 0 1310.72u). As you seen in Ramp wave,the step size is fixed because all the value are equally distributed. # Analysis of ADC DAC for Ramp

For Transfer curve we need difference Analysis:
• In DAC first I need to find value at each one step and then find DNL & INL.
• IN ADC I need to find how long the step is and its done with histogram test.
• As you see the data is big so we need a filter and filtering I used Java script that is given Read Raw File
• Here we just add the starting and ending time of the simulation and add RAW file..
• We Find Extracted values,Integers Mapping,IND,DLN and also Histogram test.

# INL & DNL Analysis of DAC for Ramp

• For this analysis i just used the given java script and get the following result that are shown in figure.
• Here First graph shows the Extracted Vales of the Ramp signal While other show INL & DNL.
• In graph Green one is ideal value while blue line shows the extracted values opf the signal.
• I have find ideal ADC and DAC curve same So the INL & DNL must be Zero.
• # ADC Histogram Test for Ramp

• For this analysis I again used the same java script and get the following result that are shown in figure.
• In Histogram test I increase the number of steps and see how many time the code digit will come at ADC Output.
• In Graph for each steps of Ramp signal INL & DNL is again Zero.
• # INL & DNL Analysis of DAC for Sine

• Again form the given Java script I find the DNL & INL of DAC.
• Here First graph shows the INL & DNL of the Sine signal.
• In graph Green shows INL while Blue shows DNL Value.
• 2nd graph showns Extracted values of the integer.
• # FFt Data Analysis of DAC for Sine

• FFT webpage By using this web page I analysis the FFT accourding to your given instruction.
• Here First graph shows the INL & DNL of the Sine signal.
• In 1st graph it shows simple sine wave form.
• 2nd graph shows the FFT analysis of the sine signal and get a limited number.
• 3rd graph shows INL & DNL.ALl values of INL is zero because of missing code.
• 4th graph shows the histogram valuse which is expected to be Zero but its not. May be it is error on Java script.
•    # Schematic & Simulation of R2R DAC

 The schematic shows a 4-Bit DAC By changing the values of Resistors I simulate a Ramp test as well as Sine. I find the INL & DNL values and discuss in next slides.

# Simulation of R2R DAC for Sine Signal

• 1st graph shows the FFT behaviour of the R2R .
• 2nd graph shows the histogram test and we see the value are not zero,its shows error in INL & DNL values.
•  # Simulation of R2R DAC for Ramp Signal

• The graph on left hand shows the extracted values of the Ramp signal .
• The graph ob Right hand shows the INL & DNL values of the Ramp signal.
• INL shows big jump at higher order bit while 2 lower jumps at least bit of the signal.
• # Summary

• 1st I Analysis the 4-Bit ADC & DAC for Sine as well as for the Ramp signal.
• By observing the analysis of schematic, I understand how conversion can take place in Analog & Digital Signal.
• I leared how to find the INL & DNL values of the signal, through these value I also able to find the SNR.
• I also learned the FFT and histogram test of the ADC
• I also used R2R circuit and again observed the behavior of 4-Bit ADC & DAC.
• I also Learned how to make web Report.

# References

 Making of a Webreport , Vollrath
 Lab03 ADC DAC Analysis , Vollrath