Overview

• Task
• Voltage Calculation
• INL and DNL
• FFT and SNR

Task

Reply 1

Task Vout(1100)

Task LSB

1. Analyze the Input Configuration for Code 0001
   • MSB Side: \(D_3 = 0\) and \(D_2 = 0 \rightarrow\) Both \(C_{3}\) and \(C_{2}\) are connected to ground (\(0\text{ V}\)).
   • LSB Side: \(D_1 = 0\) and \(D_0 = 1 \rightarrow\) \(C_{1}\) is connected to ground, while \(C_{0}\) is connected to \(V_{ref} = 4\text{ V}\).
   
2. Apply Nodal Analysis to the Left Sub-Array Node (\(V_{left}\))
   The node between the LSB capacitors and the coupling capacitor \(C_{5}\) has three components connected directly to it:
   • \(C_6 = 100\text{ nF}\) (connected to GND)
   • \(C_1 = 200\text{ nF}\) (connected to GND)
   • \(C_0 = 100\text{ nF}\) (connected to \(V_{ref}\))
   The total capacitance connected to the ground/reference side on the left is \(C_{left} = C_6 + C_1 + C_0 = 400\text{ nF}\).
   By viewing the circuit from the left node (\(V_{left}\)), the right side of the circuit (at node \(V_{int}\)) looks like a single equivalent capacitance to ground because all MSB capacitors are tied to ground:
   \(C_{right\_to\_gnd}=C_{2}+C_{3}=100\text{\ nF}+200\text{\ nF}=300\text{\ nF}\)
   The coupling capacitor \(C_5 = 100\text{ nF}\) is in series with this \(C_{right\_to\_gnd}\), creating an equivalent load on the right side of the \(V_{left}\) node:
   \(C_{load\_right}=\frac{C_{5}\cdot C_{right\_to\_gnd}}{C_{5}+C_{right\_to\_gnd}} = \frac{100\text{\ nF}\cdot 300\text{\ nF}}{100\text{\ nF}+300\text{\ nF}}=75\text{\ nF}\)
3. Determine the Voltage at the Left Node (\(V_{left}\))
   Now, treating \(V_{left}\) as a simple capacitive voltage divider driven by \(C_{0}\) to \(V_{ref}\):
   \(V_{left}=V_{ref}\cdot \frac{C_{0}}{C_{6}+C_{1}+C_{0}+C_{load\_right}}\)
   \(V_{left}=4\text{\ V}\cdot \frac{100\text{\ nF}}{100\text{\ nF}+200\text{\ nF}+100\text{\ nF}+75\text{\ nF}}=4\cdot \frac{100}{475}=\frac{16}{19}\text{\ V}\approx 0.8421\text{\ V}\)
   
4. Find the Output Voltage (\(V_{int} = V_{out}\)) via Attenuation
   The voltage at \(V_{left}\) is attenuated through the capacitive divider formed by \(C_{5}\) and the MSB capacitors (\(C_2 + C_3\)) to arrive at \(V_{int}\):
   \(V_{out}=V_{left}\cdot \frac{C_{5}}{C_{5}+C_{2}+C_{3}}\)
   \(V_{out}=\left(\frac{16}{19}\text{\ V}\right)\cdot \frac{100\text{\ nF}}{100\text{\ nF}+100\text{\ nF}+200\text{\ nF}}\)
   \(V_{out}=\frac{16}{19}\cdot \frac{100}{400}=\frac{16}{19}\cdot \frac{1}{4}=\frac{4}{19}\text{\ V}\approx \mathbf{0.2105}\text{\ V}\)
5. Verify the LSB Step Size
   Because this split-array architecture uses an attenuated scaling logic, the weights of the bits are split into fractional ratios.
   • A standard binary weight for \(D_{0}\) requires it to be half the value of \(D_{1}\).
   • In this specific non-fractional radix sizing layout, the absolute voltage output for the first digital step code 0001 yields 0.2105 V.
   • However, because the step size between consecutive codes depends on whether a transition crosses the split array (like from 0011 to 0100), this specific DAC exhibits non-linearity (DNL/INL) errors unless the scaling capacitor \(C_{5}\) is fractionally matched precisely to the radix ratio.
   Thus, the base resolution directly driven by the single LSB input switch (\(D_{0}\)) equals exactly 0.2105 V.
   Would you like to analyze the full-scale output range (code 1111) or check if this specific choice of \(C_5 = 100\text{nF}\) causes monotonicity or linearity issues in the DAC's transfer curve?
   

TASK INL, DNL

Task INL,DNL table with Videal

Task FFT, SNR, ENOB

Task FFT graph

Task FFT

Summary

• The schematic picture was succesfully analyzed
• Individual output voltages and INL, DNL can be calculated
• SNR, ENOB are correctly calculated
• An FFT graph was only created after specifying amplitude and frequency.