It is intended to study the effect of nonlinearity, offset, noise and error correction on INL,
DNL and signal to noise ratio of the spectrum of an ADC or a pipeline ADC.
It is assumed that the input range is from 0 V to 1 V.
All calculations are done with JavaScript at the client side. JavaScript source code
is available in the HTML document and can be modified as needed.
The graphs show the folding function (pipeline ADC), transfer function, histogram for a ramp,
from this calculated INL and DNL and a sine input signal with FFT.
The FFT takes a lot of time using more than 2048 points (ca. 4s).
Number of Bits (10 or more can take quite some time)
ADC converter (Regular Pipeline: 0, linear folder pipeline: 1,
nonlinear folding pipeline: 2, normal ADC: 3)
FFT signal
Number of Periods (Default: 17)
Ratio FFT points and number of codes (Default: 16)
Zoom transfer:
Start voltage
Number of samples
Pipeline ADC specific
Offset [V] (Default: 0 V)
Gain1 (Default: 2)
Gain2 (Default: 2)
Compare Level (Default: 0.5) [V]
Noise Error:
Noise
Nonlinearity Error:
Nonlinearity sine amplitude
Nonlinearity sine frequency
Nonlinearity sine Phase (0..1)
Distortion Error:
Distortion amplitude (0..1)
Distortion start (0..1)
Distortion length (0..1)
Jitter Error
Jitter standard deviation (0..0.1 sample time)
6 sigma should be less than 0.5 period
Windowing:
Pipeline AD one stage transfer function:
Transfer function:
Zoomed transfer function:
Histogramm:
INL and DNL error:
Sine time signal:
Spectral test:
SNR = 1.76 dB + 6.02 B dB + 10 log_{10}( N / 2 )
B: Number of Bits
N: Number of samples = 16 * 2 ^{ B }
N = 2048 -> 30 dB
Regular ADC
Select Number of Bits as 8, ADC converter 3, Number of periods 17 and leave Error section as it is.
This is the default setting.
Check functionality
It can be seen in the zoomed window that ideal transfer curve
and real transfer curve are matching. Each code is sampled 10 times and INL and DNL is 0.
FFT is done with 4k samples and shows a signal level of -9dB, a total noise of -59 dB and a
noise peak at 76 dB. This matches expectations since 1.76dB + 6.02 * 8 dB = -9dB - ( -59dB).
The general noise level of the FFT is lower because of the number of samples.
Run time
Increasing the number of bits from 8 to 12 shows the increase in runtime measured on a 1.3 GHz Laptop.
Number of bits
8
9
10
11
12
13
15
16
Run time [s]
1.4 (5)
1.7
2.6 (8.5)
8.5
17 (22)
34
135
(293)
Influence of Noise
In real measurements noise will be present at the input signal and the input circuit.
Good values for noise are 1/256 = 0.004, 1/1024 = 0.001, 1/4096 = 0.00025.
This can be simulated by setting noise in the error section to 0.01 and keeping the number of bits to 8.
It is very hard to see a change in the transfer function, therefore a zoom window is also displayed.
A gaussian distributed noise with a mean of 0 and a sigma of 0.01 will be added to the input signal.
A noisy signal and INL, DNL can be seen. The noise has a peak of 10 codes. 3 sigma would be 2.56 * 3 = 7.7.
Total noise increases from -59 dB to -34 dB, which is 25 dB.
Regular ideal pipeline ADC
For an ideal residue function (B = 8, Offset = 0 V, Gain1 = Gain2 = 2.0, Compare level = 0.5 V,
Pipe Stage = 0 and 17 Periods)
10 samples are generated per code and INL and DNL are 0.
The difference of level between signal of -9 dB and total noise of -59 dB is close to
SNR = 1.76 dB + 6.02 * 8 dB.
The total noise level can only be calculated adding the sum of squares.
The graph shows only noise between -76 dB and -200 dB.
-200 dB will be set, if the noise level is 0V.
Changing the number of bits will modify the signal to noise ratio.
A change to a gain of 1.99 shows a maximum INL = 1.4 LSB and DNL of -1 LSB and a noise peak of -63 dB in FFT.
A peak in FFT due to INL and DNL error shows up at 40 Hz, with -63 dB,
but is still below the total noise level of -57 dB.
Folding ideal pipeline ADC
Only Pipe Stage is set to 1 and the same results show up as the ideal ADC.
A gain of 1.99 shows a maximum INL = 1.2 LSB a DNL = -1 LSB and a noise peak of - 63 dB in FFT.
Everything is the same as in the regular pipeline ADC. The maximum INL and DNL show up at different codes.
Nonlinear folding ideal pipeline ADC
Pipe Stage is set to 2, gain is set to 2.
INL goes up to 37 LSB, INL maximum is 1.6 LSB. FFT shows a -11 dB signal, noise peak at -30 dB and total noise of -29 dB.
INL indicates that more than 5 bits are lost.
FFT gives an effective number of bits
ENOB = (29 dB - 11 dB - 1.76 dB) / 6.02 dB = 16.27 / 6.02 = 2.7.
Normal ADC: 8 Bits, maximum INL: 0, signal to noise peak: -9 dB - (-76 dB) = 68 dB,
signal to noise ratio: -9dB - (-59 dB) = 50 dB
Number of Bits
8
12
Maximum INL
27
420
Maximum occurence of code
16
16
Signal to Noise peak
-11 dB - (-30dB) = 19 dB
-11 dB - (-30dB) = 19 dB
Signal to Noise ratio
-11 dB - (-29dB) = 18 dB
-11 dB - (-29dB) = 18 dB
To investigate smaller nonlinearities Pipe Stage is set to 1, gain is set to 2.
Error Nonlinearity sine amplitude is set to 0.04 and sine frequency is set to 2.
The transfer function gets non linear.
Signal is -10 dB, INL max is 12, noise peak is -38dB and total Noise is -36 dB.
Error Nonlinearity sine amplitude is set to 0.004
Signal is -9 dB, INL max is 1.4, noise peak is -57dB and total Noise is -54 dB.
Error Nonlinearity sine amplitude is set to 0.008
Signal is -9 dB, INL max is 2.8, noise peak is -51dB and total Noise is -49 dB.
Is it possible to compensate for the non linear transfer function?
How many bits are lost?
Reduce number of bits by a factor of 2 and cut out the nonlinear edges
Remap the codes using an inverse transfer function. Use a factor of 2 or
due to the maximum occurence of 16 a factor of 1.6.
Error correction
Ideal transfer curve is monotonic increasing, with a constant slope.
What can be corrected?
Varying slope?
Negative slope?
Instructions:
Use a lookup table.
Take the highest count (HC) of codes.
Calculate LSB voltage using HC.
Divide the input range by LSB to get the number of codes.
Calculate new resolution.
Make a lookup table with calculated code and corrected code. (Display chart)
Feed sine signal with correction. (Display chart)
Next steps
1. Investigate different szenarios.
2. Implement an error correction by reducing the number of effective bits with a factor of 2.