Description
A pipeline ADC circuit is built on a PCB board and tested with the Electronic Explorer as a signal
generator and a NEXYS 3 for control signal generation and data collection.
To minimize the number of components the residue is fed back to the input via a switch.
An inifinite number of bits can be generated by serial operation.
Version 4
SHEET 1 1368 680
WIRE 96 304 64 304
WIRE 64 320 64 304
WIRE 624 336 80 336
WIRE 352 352 320 352
WIRE 352 384 352 352
WIRE 208 400 176 400
WIRE 304 400 272 400
WIRE 336 400 304 400
WIRE 416 400 368 400
WIRE 528 400 416 400
WIRE 32 416 0 416
WIRE 416 416 416 400
WIRE 624 416 624 336
WIRE 624 416 592 416
WIRE 32 432 32 416
WIRE 528 432 512 432
WIRE 16 448 -16 448
WIRE 48 448 48 336
WIRE 96 448 48 448
WIRE 112 448 96 448
WIRE 176 448 176 400
WIRE 176 448 112 448
WIRE 96 464 96 448
WIRE 416 496 416 480
WIRE 512 496 512 432
WIRE 624 496 512 496
WIRE 624 512 624 496
WIRE 176 528 176 448
WIRE 256 528 176 528
WIRE 96 544 96 528
WIRE 368 544 320 544
WIRE 624 608 624 592
FLAG 368 544 Ds0
IOPIN 368 544 Out
FLAG -16 448 A
IOPIN -16 448 In
FLAG 96 544 0
FLAG 0 416 CLK1
FLAG 304 400 res0
FLAG 112 448 sample0
FLAG 416 496 0
FLAG 320 352 CLK2
FLAG 416 400 sample1
FLAG 96 304 CLK3
FLAG 624 608 0
SYMBOL SampleHold 32 448 R0
SYMATTR InstName X1
SYMBOL cap 80 464 R0
WINDOW 0 22 8 Left 2
SYMATTR InstName C1
SYMATTR Value 4.7p
SYMBOL Comparator 288 528 R0
SYMATTR InstName X2
SYMBOL Folder 240 400 R0
SYMATTR InstName X3
SYMBOL SampleHold 352 400 R0
SYMATTR InstName X4
SYMBOL cap 400 416 R0
SYMATTR InstName C2
SYMATTR Value 4.7p
SYMBOL SampleHold 64 336 M0
SYMATTR InstName X5
SYMBOL res 608 400 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 608 496 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL Opamp1 560 416 R0
SYMATTR InstName X6
TEXT 704 232 Left 2 !.include cmosedu_models.txt\n.global vdd\nV1 Ax 0 SINE(0.466 0.06 0.0005G) AC 1\nVDD VDD 0 DC 1\nVA A 0 PULSE(0.35 0.6 0 10u 10u 0 20u)\n*VA A 0 PULSE(0.35 0.585 0 1000u 1000u 0 2000u)\nVCLK1 CLK1 0 DC 0\nVCLK2 CLK2 0 DC 0\nVCLK3 CLK3 0 DC 1\n*VCLK1 Clk1 0 PULSE(1 0 0 0.1n 0.1n 19.9n 800n)\n*VCLK2 CLK2 0 PULSE(1 0 25n 0.1n 0.1n 19.9n 80n)\n*VCLK3 CLK3 0 PULSE(1 0 50n 0.1n 0.1n 19.9n 80n)\n.tran 0 40u 0 0.1n\n* .dc VA 0 1 0.0001\n* .noise v(Y) VA dec 10 10 10G
The whole circuit is realized using 3 ALD1106 and 3 ALD1107 integrated circuits.
Version 4
SHEET 1 1984 896
WIRE -80 -112 -80 -128
WIRE -32 -112 -80 -112
WIRE 16 -112 -32 -112
WIRE -80 -80 -80 -112
WIRE 512 -64 512 -80
WIRE 560 -64 512 -64
WIRE 848 -48 848 -96
WIRE 896 -48 848 -48
WIRE -32 -32 -32 -112
WIRE -32 -32 -80 -32
WIRE 560 -16 560 -64
WIRE 560 -16 512 -16
WIRE -128 0 -144 0
WIRE 896 0 896 -48
WIRE 896 0 848 0
WIRE 464 16 432 16
WIRE -144 32 -144 0
WIRE -144 32 -176 32
WIRE -80 32 -80 16
WIRE -80 32 -144 32
WIRE -32 32 -80 32
WIRE 800 32 784 32
WIRE 976 48 848 48
WIRE -176 64 -176 32
WIRE -32 64 -32 32
WIRE 176 64 176 16
WIRE 432 80 432 16
WIRE 512 80 512 32
WIRE 512 80 432 80
WIRE 784 96 784 32
WIRE 832 96 784 96
WIRE 976 96 976 48
WIRE 976 96 912 96
WIRE -176 112 -256 112
WIRE 16 112 16 -112
WIRE 16 112 -32 112
WIRE 160 112 128 112
WIRE 272 112 256 112
WIRE 592 128 544 128
WIRE 688 128 672 128
WIRE 736 128 688 128
WIRE 784 128 784 96
WIRE 784 128 736 128
WIRE -112 144 -112 112
WIRE -112 144 -128 144
WIRE -80 144 -112 144
WIRE 208 144 208 112
WIRE 976 144 976 96
WIRE 976 144 848 144
WIRE 1056 144 976 144
WIRE 512 160 512 80
WIRE 544 160 544 128
WIRE 544 160 512 160
WIRE 688 160 688 128
WIRE -176 176 -176 160
WIRE -80 176 -176 176
WIRE -32 176 -32 160
WIRE -32 176 -80 176
WIRE 16 176 -32 176
WIRE 512 176 512 160
WIRE 16 192 16 176
WIRE 128 192 128 112
WIRE 128 192 16 192
WIRE 272 192 272 112
WIRE 304 192 272 192
WIRE 368 192 304 192
WIRE 416 192 368 192
WIRE 928 192 848 192
WIRE 304 208 304 192
WIRE 336 208 304 208
WIRE -576 224 -576 192
WIRE -80 224 -160 224
WIRE 560 224 512 224
WIRE 784 224 784 128
WIRE 800 224 784 224
WIRE 128 240 128 192
WIRE 160 240 128 240
WIRE 208 240 208 224
WIRE 272 240 272 192
WIRE 272 240 256 240
WIRE 848 240 688 240
WIRE 928 240 928 192
WIRE 928 240 848 240
WIRE 16 256 16 192
WIRE 16 256 -32 256
WIRE 416 256 416 192
WIRE 464 256 416 256
WIRE -592 272 -624 272
WIRE -480 272 -496 272
WIRE -256 272 -256 112
WIRE -160 272 -160 224
WIRE -160 272 -256 272
WIRE -80 272 -160 272
WIRE 560 272 560 224
WIRE 560 272 512 272
WIRE 848 272 848 240
WIRE -544 304 -544 272
WIRE -80 304 -80 272
WIRE 512 304 512 272
WIRE 240 320 240 288
WIRE 336 320 336 272
WIRE -480 352 -480 272
WIRE -432 352 -480 352
WIRE -624 368 -624 272
WIRE -624 368 -704 368
WIRE -624 400 -624 368
WIRE -592 400 -624 400
WIRE -544 400 -544 384
WIRE -480 400 -480 352
WIRE -480 400 -496 400
WIRE -96 416 -96 400
WIRE -48 416 -96 416
WIRE 80 416 64 416
WIRE 224 416 224 400
WIRE 224 416 160 416
WIRE 656 416 656 368
WIRE 704 416 656 416
WIRE 848 416 848 368
WIRE 896 416 848 416
WIRE 224 448 224 416
WIRE 272 448 224 448
WIRE -48 464 -48 416
WIRE -48 464 -96 464
WIRE 704 464 704 416
WIRE 704 464 656 464
WIRE 896 464 896 416
WIRE 896 464 848 464
WIRE -512 480 -512 448
WIRE -144 496 -176 496
WIRE 272 496 272 448
WIRE 272 496 224 496
WIRE 608 496 592 496
WIRE 800 496 784 496
WIRE 176 528 160 528
WIRE 512 528 320 528
WIRE -176 544 -176 496
WIRE -96 544 -96 512
WIRE -96 544 -176 544
WIRE 848 544 848 512
WIRE 944 544 848 544
WIRE -576 560 -576 544
WIRE 656 560 656 512
WIRE 784 560 784 496
WIRE 784 560 656 560
WIRE 224 576 224 544
WIRE 320 576 320 528
WIRE 320 576 224 576
WIRE 400 576 352 576
WIRE 512 576 512 528
WIRE 512 576 480 576
WIRE 592 576 592 496
WIRE 592 576 512 576
WIRE 656 592 656 560
WIRE 848 592 848 544
WIRE -592 608 -624 608
WIRE -480 608 -496 608
WIRE 64 608 64 416
WIRE 160 608 160 528
WIRE 160 608 64 608
WIRE 352 608 352 576
WIRE 352 608 160 608
WIRE 224 624 224 576
WIRE -544 640 -544 608
WIRE -96 640 -96 544
WIRE -64 640 -96 640
WIRE 32 640 16 640
WIRE 64 640 64 608
WIRE 64 640 32 640
WIRE 736 640 656 640
WIRE 928 640 848 640
WIRE -96 656 -96 640
WIRE 304 672 224 672
WIRE 592 672 592 576
WIRE 608 672 592 672
WIRE 784 672 784 560
WIRE 800 672 784 672
WIRE -624 688 -624 608
WIRE -624 688 -704 688
WIRE -480 688 -480 608
WIRE -432 688 -432 352
WIRE -432 688 -480 688
WIRE -384 688 -432 688
WIRE -368 688 -384 688
WIRE -304 688 -368 688
WIRE 736 688 736 640
WIRE 736 688 656 688
WIRE 928 688 928 640
WIRE 928 688 848 688
WIRE -16 704 -96 704
WIRE 160 704 160 608
WIRE 176 704 160 704
WIRE 32 720 32 640
WIRE 48 720 32 720
WIRE 224 720 128 720
WIRE 304 720 304 672
WIRE 304 720 224 720
WIRE 656 720 656 688
WIRE 848 720 848 688
WIRE -624 736 -624 688
WIRE -592 736 -624 736
WIRE -544 736 -544 720
WIRE -480 736 -480 688
WIRE -480 736 -496 736
WIRE -144 736 -192 736
WIRE -16 752 -16 704
WIRE -16 752 -96 752
WIRE 224 752 224 720
WIRE -96 784 -96 752
WIRE -368 800 -368 752
WIRE -512 816 -512 784
FLAG 512 304 0
FLAG -80 304 0
FLAG 512 -80 VDD
FLAG -112 112 a
IOPIN -112 112 In
FLAG 16 176 a1
FLAG -80 -128 Vdd
FLAG 848 272 0
FLAG 848 -96 Vdd
FLAG 544 160 a3
FLAG -192 736 a
IOPIN -192 736 In
FLAG 1056 144 y1
IOPIN 1056 144 Out
FLAG -96 784 0
FLAG -96 400 VDD
FLAG 224 752 0
FLAG 224 400 Vdd
FLAG 944 544 D
IOPIN 944 544 Out
FLAG -368 800 0
FLAG 208 144 VDD
FLAG 208 224 0
FLAG -304 688 a
FLAG -544 640 VDD
FLAG -544 720 0
FLAG -544 304 VDD
FLAG -544 384 0
FLAG -704 368 In
FLAG -704 688 Y1
FLAG -576 192 C1
FLAG 176 16 C2b
FLAG 240 320 C2
FLAG -384 688 y1x
FLAG -512 480 C1b
FLAG -576 544 C3b
FLAG -512 816 C3
FLAG 656 720 0
FLAG 656 368 Vdd
FLAG 848 720 0
FLAG 848 368 Vdd
FLAG 336 320 0
FLAG 368 192 a2
FLAG 736 128 a4
SYMBOL nmos4 464 176 R0
SYMATTR InstName M1
SYMATTR Value N
SYMBOL pmos4 -128 -80 R0
SYMATTR InstName M3
SYMATTR Value P
SYMBOL nmos4 -32 176 M0
SYMATTR InstName M4
SYMATTR Value N
SYMBOL nmos4 -128 64 M0
SYMATTR InstName M5
SYMATTR Value N
SYMBOL pmos4 -80 64 R0
SYMATTR InstName M6
SYMATTR Value P
SYMBOL nmos4 800 144 R0
SYMATTR InstName M8
SYMATTR Value N
SYMATTR Value2 m=8
SYMBOL pmos4 800 -48 R0
SYMATTR InstName M9
SYMATTR Value P
SYMATTR Value2 m=8
SYMBOL pmos4 464 -64 R0
SYMATTR InstName M2
SYMATTR Value P
SYMBOL nmos4 -144 656 R0
SYMATTR InstName M7
SYMATTR Value N
SYMBOL nmos4 176 624 R0
SYMATTR InstName M10
SYMATTR Value N
SYMBOL pmos4 176 448 R0
SYMATTR InstName M11
SYMATTR Value P
SYMBOL res 496 560 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 300k
SYMBOL res 32 624 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 20k
SYMBOL res 64 432 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 20k
SYMBOL pmos4 -144 416 R0
SYMATTR InstName M12
SYMATTR Value P
SYMBOL res 32 736 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 16.051k
SYMBOL cap -384 688 R0
SYMATTR InstName C1
SYMATTR Value 0.5p
SYMBOL pmos4 256 64 R90
SYMATTR InstName M13
SYMATTR Value P
SYMBOL nmos4 160 288 R270
WINDOW 0 65 24 Left 2
SYMATTR InstName M14
SYMATTR Value N
SYMBOL pmos4 -496 560 R90
SYMATTR InstName M15
SYMATTR Value P
SYMBOL nmos4 -592 784 R270
SYMATTR InstName M16
SYMATTR Value N
SYMBOL pmos4 -496 224 R90
SYMATTR InstName M17
SYMATTR Value P
SYMATTR Value2 m=8
SYMBOL nmos4 -592 448 R270
SYMATTR InstName M18
SYMATTR Value N
SYMATTR Value2 m=8
SYMBOL res 688 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 672 144 R0
SYMATTR InstName R2
SYMATTR Value 28k
SYMBOL res 928 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 118.8344k
SYMBOL nmos4 608 592 R0
SYMATTR InstName M19
SYMATTR Value N
SYMBOL pmos4 608 416 R0
SYMATTR InstName M20
SYMATTR Value P
SYMBOL nmos4 800 592 R0
SYMATTR InstName M21
SYMATTR Value N
SYMBOL pmos4 800 416 R0
SYMATTR InstName M22
SYMATTR Value P
SYMBOL cap 320 208 R0
SYMATTR InstName C2
SYMATTR Value 0.5p
TEXT 48 -168 Left 2 ;-- Folder\n-- 2 CD4007\n-- 2 ALD 1106/1107
TEXT 304 392 Left 2 ;-- Comparator\n-- 1 CD4007\n-- 1/2 ALD 1106, 1107
TEXT -376 336 Left 2 ;-- Sample and Hold
TEXT -720 -368 Left 2 !*VC1 C1 0 DC 0\n*VC1b C1b 0 DC 1\n*VC2 C2 0 DC 4\n*VC2b C2b 0 DC 0\n*VC3 C3 0 DC 0\n*VC3b C3b 0 DC 4\n*VIN A 0 PULSE(0 4 0 200000n 200000n 0 400000n)\nVIN IN 0 PULSE(1.1 2.4 0 4000u 4000u 0 8000u)\nVC3b C3b 0 PULSE(3.3 0 260n 10p 10p 99.98n 400n)\nVC3 C3 0 PULSE(0 3.3 260n 10p 10p 99.98n 400n)\nVC2 C2 0 PULSE(0 3.3 130n 10p 10p 99.98n 400n)\nVC2b C2b 0 PULSE(3.3 0 130n 10p 10p 99.98n 400n)\nVC1b C1b 0 PULSE(0 3.3 0 10p 10p 99.98n 3600n)\nVC1 C1 0 PULSE(3.3 0 0 10p 10p 99.98n 3600n)
TEXT 168 -264 Left 2 !;ALD1106N\n.model N NMOS(LEVEL=1 KP=0.48m VT0=0.7 LAMBDA=0.018 CGDO=100n CGSO=100n)\n; ALD1107P\n.model P PMOS(LEVEL=1 KP=0.2m VT0=-0.7 LAMBDA=0.018 CGDO=100n CGSO=100n)
TEXT 192 24 Left 2 ;-- Sample and Hold
TEXT -472 240 Left 2 ;U1P2
TEXT -704 464 Left 2 ;U1N1
TEXT 272 72 Left 2 ;U2P3
TEXT -680 560 Left 2 ;U2P2
TEXT -672 784 Left 2 ;U2N1
TEXT 120 312 Left 2 ;U2N4
TEXT -288 72 Left 2 ;U3N4
TEXT -208 -416 Left 2 !.option plotwinsize=0\n.global vdd\nVDD VDD 0 DC 4\n.tran 0 4000u 0 1n\n*step size 1n gives 400 000 points static up down, 12uV resolution\n* .dc VA 0 1 0.0001\n* .noise v(Y) VA dec 10 10 10G
Figure 1: Circuit diagram (Click on picture to see LTSPICE drawing code)
The left shows the sample and hold switches selecting the external signal or the internal residue for
serial conversion.
The top shows the signal path with the second sample and hold after the folder and
before the second amplifier.
The signal path is buffered with 0.5pF.
The power supply is buffered with 474nF.
The bottom path shows the digital path to compare the input signal.
Both paths are calibrated with potentiometers replacing R1,R2 and R4, R5.
There are 2 potentiometers each, one for offset and one for gain.
These are the blue blocks. On the left are potentiometers for comparator offset and comparator gain.
On the right are potentiometers for amplifier offset and amplifier gain.
Figure 2: System picture
The top shows the pipeline ADC PCB on top of the Electronic Explorer.
The Electronic Explorer provides power VP+=4V and the ramp signal via AWG1 as
triangle from 0V to 4V.
The NEXYS3 connector JA1 is used as interface to the pipeline ADC.
Figure 3: PMOD connector
JA connector
| JA Pin 1 | JA Pin 2 | JA Pin 3 | JA Pin 4 |
JA Pin 7 | JA Pin 8 | JA Pin 9 |
| C3 | C3b | C2 | C2b | C1b | C1 | Data out |
A terminal can be connected to the second USB port to acquire data via Hyperterm.
Baud rate is 38400.
In Windows the terminal application has to be started a couple of times until it works.
Figure 4: USB-UART connector
The switches are used for different settings:
| switch (sw4) | = 1 controls static TGs or dynamic TGs |
| switch (3 downto 0) one sample time (switch pulse) | control pulsewidth and sample rate |
| 0000 | 5400ms |
| 0001 | 340ms |
| 0010 2.6 ms (1.14 ms) | 84ms fs= 11Hz 32 Bit -> 32 times value UART sent |
| 0011 655 us (282 us) | 22ms -> fs= 46Hz 32 Bit -> 8 times UART sent |
| 0100 325 us (140 us) | 11ms |
| 0101 162 us (70 us) not working | 5ms |
| 0110 50us | 2.5ms |
| 0111 | 1.25ms |
| switch (5 downto 6) control number of bits |
| 00 | 32 |
| 01 | 16 |
| 10 | 8 |
| 11 | 2 |
| switch (7) dual data strobe for 2 boards connected |
| btn(0) | B8 reset |
| btn(1) | activate average |
For 0010 the pulse is 1.14 ms low and has a 1.31 ms cycle. 2 Pulses are needed for 1 bit.
The external voltage is connected for 2 pulses and then clk3 and 2 are used alternating.
This gives 2.6 ms per Bit and 84ms for 32 Bits.
At 0101 not working any more.
Measurement
Load sigma_nexys3.bit into NEXYS 3 Board.
Calibration of residue and digital comparator
Switch 4 should be on (slide up) for static measurement for calibration.
This gives the following signal levels.
| C1 | C1b | C2 | C2b | C3 | C3b |
| 0 | 1 | 1 | 0 | 0 | 1 |
| switch open | switch closed | switch closed |
The input signal is passed through the folder and amplifier.
Start Waveforms.
VP+ is 4V and current limit 100mA.
Wavegenerator activates AWG1, triangle, 1kHZ, Offset 2V, Amplitude 1V.
Start oscilloscope: 200us/div, 1V/div, Trigger channel 1 (triangel),
channel 2 residue, channel 4 folder output.
Measure the residue with an oscilloscope.
If there is a phase shift between residue and output reduce the frequency.
Frequency: 1Hz. Oscilloscope: 50ms/div (Triggering ok)
Figure: Static characteristic of a folding pipeline ADC
C1 is the input ramp, C2 is the residue, C3 is the comparator output
and C4 the folded signal.
Looking at the cursors shows: 2 V input signal (C1) gives 250 mV folder output (C4)
and is amplified to 2 V output (C2) with a gain of 8.
Since the folder output has a average value of 0.75 V it has to be shifted to 2 V
for the next gain stage.
First the comparator has to be calibrated. The code for a signal a little below
midpoint has to be the same as above midpoint.
The switch for 24 bit operation at mid level should ideally be between x7FFFFF to x800000.
For calibration look at the transfer of an input signal where the residue is minimum
and make sure that the resulting signal is not going out of the box.
Step by step calibration is done by increasing gain and then adjusting offset.
The minimum can not be to low since the curve will get very flat at the minimum and can limit overall resolution.
A real circuit needs for autocalibration a comparator for low level and high level at some stages and
offset and gain control. The offset and gain control has to be very precise, comparable to pipeline ADC resolution.
The cursors show the transfer characteristic of an input signal.
The minimum of the residue is given by the W/L ratio of the folder. It occurs for a certain input level
and can not be changed. This input level is half the input range.
An input signal of this (Example: 1.825V) will generate a residue of 0.740V.
An input signal of 0.740V will generate a residue of 2.63V.
An input signal of 2.63V will generate a residue of 2.63V.
If the last step results in a higher voltage runaway will occur and bits are lost.
If the last step is a lower voltage the voltage will decrease slowly and bits are lost.
The input range is from 0.74V to 2.63V, which gives 1.89V range.
Save the transfer function in an ASCII file to be able to simulate the ADC.
Unfortunately during switch operation the transfer function will change due to charge coupling
and incomplete charging of capacitors. Charge coupling can affect the signal in both direction.
Incomplete charging can dampen the signal and prevent runaway.
Increasing the ramp frequency shows the delay of the signal path:
100Hz -> 100us.
1kHz -> 90us.
The delay of the comparator is much smaller: 12us.
Figure : Delay of an input signal
Ramp measurement
Switch 4 down 0 to enable dynamic operation.
Switch (3 downto 0) = 0011 gives a clk cycle of 2.05 ms and a sample rate of 84ms.
switch (5 downto 6) = 00 to generate 32 bits. Only 24 bits are transfered via UART.
The clocks look as follows:
With C1 the external signal In is transfered to the first capacitance C1 of the sample and hold.
C2 transfers the result of the folder to the second capacitance C2 of the second sample and hold.
The amplified signal is fed back to the first capacitance C1.
The simulation picture shows 9 bits before a new external sample In is taken.
For 16Bit resolution at least 65k measurement points are needed. Since the
Electronic Explorer DAC has 14 Bit or 16k values this is a little bit too much.
Start Hyperterminal and identify COM port (USB Com port).
For this system it was COM19 with a protocol of: Bit Rate 38400,8,none,1,hardware.
Since it didn't work, the device manager (Gerätemanager) was checked for COM19 and
Hyperterminal was restarted with a new connection.
A ramp of 1mHz needs 500s = 8.5 min per edge. With a sample rate of 90ms this gives 5000 values.
A ramp of 200uHz needs 2500s = 40 min per edge and gives 25000 values.
Log File: 2015_04_24 (2.3MB)
Start Line 6537, 8 lines per value (84ms), End line 225594
Figure: Oscilloscope picture of sampling
The green C4 shows the sampling of external data.
The yellow C1 shows the input voltage ramp.
The blue C2 shows the residue.
On the bottom the digital out signal is displayed.
The log file:
Log File: 2015_04_24_positiveramp (2.3MB)
can be evaluated with: FFT with Calibration
A transfer characteristic measurement of a ramp shows noise, non linearities and code jumps.
Non linearities and code jumps can be calibrated. Noise has to be eliminated with circuit modifications
or can be filtered resulting in lower bandwidth.
Filtering the UART log file for unique values gives 27384 value.
The transfer characteristics shows nonlinear behaviour and jumps, due to non ideal calibration.
Consecutive values can vary a lot due to noise.
Since calibration is difficult with the real board an ideal mapping is done by
sorting the values and associating increasing numbers to it.
Lookup of 25824 unique values takes in Excel a long time.
The improved curve has less range and is more linear.
Creating columns Min, Max, Median allows estimation of noise (Max-Min).
First Looking at 16 Bits:
A maximum delta between Max and Min gives 731 (noise).
Dividing 25824 by 731 gives 35.3 steps and ENOB = 5.
The maximum noise appears at the first stage switching point.
Second Looking at 12 Bits:
A maximum delta between Max and Min gives 63 with 3378 unique codes.
Dividing 3378 by 63 gives 53.6 steps and ENOB = 5.7.
Maximum number of same codes is 218.
Having 27384 samples of input ramp gives 125.6 levels and ENOB=7.76.
The maximum noise appears at the first stage switching point.
This is a very low resolution below expectation. The resolution is limited by noise.
So lets try averaging 4 values with 12 Bits resolution.
Second Looking at 12 Bits with 4 values averaging:
A maximum delta between Max and Min gives 35 with 3561 unique codes.
Dividing 3561 by 35 gives 101.7 steps and ENOB = 6.7.
Maximum number of same codes is 238.
Having 27384 samples of input ramp gives 115 levels and ENOB=7.8.
Second Looking at 12 Bits with 8 values averaging:
A maximum delta between Max and Min gives 23 with 3411 unique codes.
Dividing 3411 by 23 gives 148.3 steps and ENOB = 7.2.
Maximum number of same codes is 148.
Having 27384 samples of input ramp gives 185 levels and ENOB=7.2.
Calibration
After analysis of possible number of bits a lookup table can be generated
for error correction.
A final lookup table (FLT) is generated looking at the maximum of the AVG8 values in a given
input ramp range.
The resulting code looks up the average of 8 values (AWG) in the final lookup table (FLT).
Figure: Transfer, INL and DNL curves
The INL and DNL curve shows a 7 bit resolution.
X Axis has more than 128 levels. Maximum INL and DNL is about 1.
Planned Improvements
Investigate relationship between non linear transfer characteristics INL, DNL and spectral test.
Investigate and optimize calibration using precision resistors.
An averaging and error correction routine and lookup in the fpga to generate correct (best) data.
A low level comparator and high level comparator for calibration should be integrated.
A second sampling circuit connected at the input could shift the input signal by
a certain amount shifting the flat regions of the transfer characteristics and improving resolution.
A new FPGA control circuit is needed.
Investigate LTSPICE simulation data processing.
Appendix
Performance of ALD1106, ALD1107
Measurement of ring oscillator:
| VDD | 2 V | 3 V | 4 V | 5 V |
| fring3 | 605 kHz | 1.88 MHz | 2.4 MHz | 2.9 MHz |
| Tring3 | 1.65 ns | 0.53 ns | 0.42 ns | 0.34 ns |
Inverter as amplifier (VDD = 5 V, T = 22 C):
| f | 100 kHz | 200 kHz | 500 kHz | 1 MHz |
| Vin | 50 mV | 50 mV | 100 mV | 100 mV |
| Vout | 1 V | 700 mV | 600 mV | 300 mV |
Capacitive load: 471 (470 pF) 100ns delay increases to 800ns delay.
NFET source circuit with PFET diode load
| f | 100 kHz | 200 kHz | 500 kHz | 1 MHz |
| Vin | 310mV | 310 mV | 310 mV | 305 mV |
| Vout | 545 mV | 540 mV | 490 mV | 400 mV |
NFET source circuit with double length PFET diode load
| f | 100 kHz | 200 kHz | 500 kHz | 1 MHz | 1 MHz |
| Vin | 110mV | 100 mV | 100 mV | 100 mV | 400 mV |
| Vout | 270 mV | 270 mV | 230 mV | 170 mV | 600 mV |
Folder 4 transistors:
| fin | 100 kHz | 200 kHz | 500 kHz | 1 MHz | 1 MHz |
| Vin | 1.5 V | | | | |
| Vout | 0.25 V | | | | |
Vin 1.5 V amplitude gives at output 250 mV. At higher frequencies the midpoint low voltage
at the output is different between rising and falling.
Difference of minimum: 500 kHz 230 mV, 100kHz 70mV, 10kHz 0 V.
Gain: 0.17
(simulation gain: 325 mV /1.5 V = 0.22)
Folder 3 transistors:
Vin 2.5V amplitude, 2.5 V offset, Vout 500 mV amplitude, 1.7 V offset, 10 kHz.
No difference between rising and falling input signal for minimum voltage at the output.
Gain: 0.2
100 kHz Minimum difference for output with rising and falling input signal is 40 mV.
1 MHz gives 285 mV difference at the minimum.
( simulation gain: 0.6 V / 2.5 V = 0.24)
|
Version 4
SHEET 1 1984 1652
WIRE -432 -96 -976 -96
WIRE -816 -48 -864 -48
WIRE -688 -48 -816 -48
WIRE -640 -48 -688 -48
WIRE -528 -48 -640 -48
WIRE -480 -48 -528 -48
WIRE -816 0 -816 -48
WIRE -816 0 -864 0
WIRE -640 0 -640 -48
WIRE -640 0 -688 0
WIRE -480 0 -480 -48
WIRE -480 0 -528 0
WIRE -912 32 -928 32
WIRE -736 32 -752 32
WIRE -576 32 -592 32
WIRE -976 48 -976 -96
WIRE -928 48 -928 32
WIRE -928 48 -976 48
WIRE -752 48 -752 32
WIRE -752 48 -864 48
WIRE -592 48 -592 32
WIRE -592 48 -688 48
WIRE -432 48 -432 -96
WIRE -432 48 -528 48
WIRE -384 48 -432 48
WIRE -864 64 -864 48
WIRE -688 64 -688 48
WIRE -528 64 -528 48
WIRE -784 112 -864 112
WIRE -608 112 -688 112
WIRE -448 112 -528 112
WIRE -928 144 -928 48
WIRE -912 144 -928 144
WIRE -752 144 -752 48
WIRE -736 144 -752 144
WIRE -592 144 -592 48
WIRE -576 144 -592 144
WIRE -784 160 -784 112
WIRE -784 160 -864 160
WIRE -608 160 -608 112
WIRE -608 160 -688 160
WIRE -448 160 -448 112
WIRE -448 160 -528 160
WIRE -864 192 -864 160
WIRE -688 192 -688 160
WIRE -528 192 -528 160
WIRE -848 352 -896 352
WIRE -816 352 -848 352
WIRE -672 352 -720 352
WIRE -624 352 -672 352
WIRE -848 400 -848 352
WIRE -848 400 -896 400
WIRE -624 400 -624 352
WIRE -624 400 -672 400
WIRE -944 432 -960 432
WIRE -720 432 -752 432
WIRE -960 464 -960 432
WIRE -960 464 -976 464
WIRE -896 480 -896 448
WIRE -816 480 -896 480
WIRE -752 480 -752 432
WIRE -672 480 -672 448
WIRE -672 480 -752 480
WIRE -640 480 -672 480
WIRE -672 496 -672 480
WIRE -816 528 -896 528
WIRE -592 544 -672 544
WIRE -960 560 -960 464
WIRE -944 560 -960 560
WIRE -816 576 -816 528
WIRE -816 576 -896 576
WIRE -720 576 -736 576
WIRE -592 592 -592 544
WIRE -592 592 -672 592
WIRE -896 608 -896 576
WIRE -672 624 -672 592
WIRE -480 656 -480 640
WIRE -432 656 -480 656
WIRE -384 656 -432 656
WIRE -480 688 -480 656
WIRE -768 736 -816 736
WIRE -736 736 -768 736
WIRE -432 736 -432 656
WIRE -432 736 -480 736
WIRE -528 768 -544 768
WIRE -768 784 -768 736
WIRE -768 784 -816 784
WIRE -544 800 -544 768
WIRE -544 800 -576 800
WIRE -480 800 -480 784
WIRE -480 800 -544 800
WIRE -432 800 -480 800
WIRE -64 800 -64 784
WIRE -64 800 -160 800
WIRE -16 800 -64 800
WIRE 32 800 -16 800
WIRE -864 816 -896 816
WIRE -576 832 -576 800
WIRE -432 832 -432 800
WIRE -160 832 -160 800
WIRE -16 832 -16 800
WIRE -768 880 -768 784
WIRE -768 880 -816 880
WIRE -576 880 -656 880
WIRE -384 880 -384 656
WIRE -384 880 -432 880
WIRE -160 880 -240 880
WIRE 32 880 32 800
WIRE 32 880 -16 880
WIRE -896 912 -896 816
WIRE -864 912 -896 912
WIRE -512 912 -512 880
WIRE -512 912 -528 912
WIRE -480 912 -512 912
WIRE -96 912 -96 880
WIRE -96 912 -112 912
WIRE -64 912 -96 912
WIRE -896 928 -896 912
WIRE -816 928 -896 928
WIRE -784 928 -816 928
WIRE -816 944 -816 928
WIRE -576 944 -576 928
WIRE -480 944 -576 944
WIRE -432 944 -432 928
WIRE -432 944 -480 944
WIRE -384 944 -432 944
WIRE -336 944 -384 944
WIRE -160 944 -160 928
WIRE -64 944 -160 944
WIRE -16 944 -16 928
WIRE -16 944 -64 944
WIRE 32 944 -16 944
WIRE 80 944 32 944
WIRE -736 992 -816 992
WIRE -480 992 -560 992
WIRE -64 992 -144 992
WIRE -864 1024 -912 1024
WIRE -384 1024 -384 944
WIRE -384 1024 -432 1024
WIRE 32 1024 32 944
WIRE 32 1024 -16 1024
WIRE -736 1040 -736 992
WIRE -736 1040 -816 1040
WIRE -656 1040 -656 880
WIRE -560 1040 -560 992
WIRE -560 1040 -656 1040
WIRE -480 1040 -560 1040
WIRE -240 1040 -240 880
WIRE -144 1040 -144 992
WIRE -144 1040 -240 1040
WIRE -64 1040 -144 1040
WIRE -816 1072 -816 1040
WIRE -480 1072 -480 1040
WIRE -64 1072 -64 1040
FLAG -480 1072 0
FLAG -512 880 a1
IOPIN -512 880 In
FLAG -336 944 y4
IOPIN -336 944 Out
FLAG -480 640 Vdd
FLAG -896 608 0
FLAG -816 352 Vdd
FLAG -736 576 a1
IOPIN -736 576 In
FLAG -816 480 y1
IOPIN -816 480 Out
FLAG -672 624 0
FLAG -720 352 VDD
FLAG -976 464 a1
IOPIN -976 464 In
FLAG -640 480 y2
IOPIN -640 480 Out
FLAG -912 1024 a1
IOPIN -912 1024 In
FLAG -816 1072 0
FLAG -736 736 VDD
FLAG -784 928 y3
IOPIN -784 928 Out
FLAG -864 192 0
FLAG -688 192 0
FLAG -688 -48 Vdd
FLAG -528 192 0
FLAG -384 48 Y0
FLAG -64 1072 0
FLAG -96 880 a1
IOPIN -96 880 In
FLAG 80 944 y5
IOPIN 80 944 Out
FLAG -64 784 Vdd
SYMBOL pmos4 -528 688 R0
SYMATTR InstName M3
SYMATTR Value P
SYMBOL nmos4 -432 944 M0
SYMATTR InstName M4
SYMATTR Value N
SYMBOL nmos4 -528 832 M0
SYMATTR InstName M5
SYMATTR Value N
SYMBOL pmos4 -480 832 R0
SYMATTR InstName M6
SYMATTR Value P
SYMBOL nmos4 -944 480 R0
SYMATTR InstName M8
SYMATTR Value N
SYMATTR Value2 m=8
SYMBOL pmos4 -944 352 R0
SYMATTR InstName M9
SYMATTR Value P
SYMATTR Value2 m=8
SYMBOL nmos4 -720 496 R0
SYMATTR InstName M7
SYMATTR Value N
SYMBOL pmos4 -720 352 R0
SYMATTR InstName M12
SYMATTR Value P
SYMBOL nmos4 -864 944 R0
SYMATTR InstName M1
SYMATTR Value N
SYMBOL pmos4 -864 736 R0
SYMATTR InstName M2
SYMATTR Value P
SYMBOL pmos4 -864 832 R0
SYMATTR InstName M10
SYMATTR Value P
SYMBOL nmos4 -912 64 R0
SYMATTR InstName M11
SYMATTR Value N
SYMATTR Value2 m=8
SYMBOL pmos4 -912 -48 R0
SYMATTR InstName M13
SYMATTR Value P
SYMATTR Value2 m=8
SYMBOL nmos4 -736 64 R0
SYMATTR InstName M14
SYMATTR Value N
SYMATTR Value2 m=8
SYMBOL pmos4 -736 -48 R0
SYMATTR InstName M15
SYMATTR Value P
SYMATTR Value2 m=8
SYMBOL nmos4 -576 64 R0
SYMATTR InstName M16
SYMATTR Value N
SYMATTR Value2 m=8
SYMBOL pmos4 -576 -48 R0
SYMATTR InstName M17
SYMATTR Value P
SYMATTR Value2 m=8
SYMBOL nmos4 -16 944 M0
SYMATTR InstName M19
SYMATTR Value N
SYMBOL nmos4 -112 832 M0
SYMATTR InstName M20
SYMATTR Value N
SYMBOL pmos4 -64 832 R0
SYMATTR InstName M21
SYMATTR Value P
TEXT -448 352 Left 2 !.option plotwinsize=0\n.global vdd\nVDD VDD 0 DC 4\n*VA1 A1 0 Sine(1.7 0.1 100k) AC 1\n*VA1 A1 0 Sine(1.5 1.5 100k) AC 1\nVA1 A1 0 Sine(2.5 2.5 100k) AC 1\n.tran 0 40u 0 1n\n;.dc VA 0 1 0.0001\n;ac dec 10 1 1G\n* .noise v(Y) VA dec 10 10 10G
TEXT -1016 224 Left 2 !;ALD1106N\n.model N NMOS(LEVEL=1 KP=0.48m VT0=0.7 LAMBDA=0.018 CGDO=100n CGSO=100n)\n; ALD1107P\n.model P PMOS(LEVEL=1 KP=0.2m VT0=-0.7 LAMBDA=0.018 CGDO=100n CGSO=100n)
TEXT -1008 664 Left 2 ;Inverter Amplifier
TEXT -784 664 Left 2 ;NFET source with diode
TEXT -1008 1120 Left 2 ;NFET source with double length PFET diode
TEXT -528 1112 Left 2 ;Folder 4 transistors
TEXT -184 1112 Left 2 ;Folder 3 transistors
|
Supply voltage variations directly go into signal: gain = 1
Power supply rejection ratio is PSRR = 0 dB.
Version 4
SymbolType BLOCK
LINE Normal -7 0 -16 0
LINE Normal 7 0 16 0
LINE Normal -7 -8 7 0
LINE Normal 0 -4 0 -16
PIN 0 -16 NONE 8
PINATTR PinName CLK
PINATTR SpiceOrder 1
PIN -16 0 NONE 8
PINATTR PinName A
PINATTR SpiceOrder 2
PIN 16 0 NONE 8
PINATTR PinName B
PINATTR SpiceOrder 3
Version 4
SymbolType BLOCK
LINE Normal -31 47 -31 -16
LINE Normal 33 16 -31 47
LINE Normal -31 -16 33 16
LINE Normal -18 5 -18 -4
LINE Normal -23 0 -13 0
LINE Normal -12 32 -22 32
TEXT -99 32 Left 0 Vdd/2
WINDOW 0 0 -24 Bottom 0
PIN -32 0 NONE 8
PINATTR PinName a
PINATTR SpiceOrder 1
PIN 32 16 NONE 8
PINATTR PinName D
PINATTR SpiceOrder 2
Version 4
SymbolType BLOCK
LINE Normal 0 -12 -15 15
LINE Normal 15 15 0 -12
RECTANGLE Normal -32 -24 32 24
WINDOW 0 0 -24 Bottom 0
PIN -32 0 NONE 8
PINATTR PinName a
PINATTR SpiceOrder 1
PIN 32 0 NONE 8
PINATTR PinName Y
PINATTR SpiceOrder 2
Version 4
SymbolType BLOCK
LINE Normal -32 32 -32 -31
LINE Normal 32 0 -32 32
LINE Normal -33 -32 32 0
LINE Normal -11 -16 -25 -16
LINE Normal -19 -10 -19 -21
LINE Normal -9 16 -23 16
WINDOW 0 0 -40 Bottom 2
PIN -32 16 NONE 8
PINATTR PinName M
PINATTR SpiceOrder 1
PIN -32 -16 NONE 8
PINATTR PinName P
PINATTR SpiceOrder 2
PIN 32 0 NONE 8
PINATTR PinName Y
PINATTR SpiceOrder 3