After getting the output from DAC we extract data from a raw file given on the webpage.
First, we set the start, stop time and time step, which are 0, 655.36µs, 40.96µs respectively.
Then we browse 4bit_ADC_DAC_pipe.raw file.
We'll get a nice DAC output curve which is same as ideal. This curve is only for output not with the input, so in the
simulation we have to write .save V(vout).
After that, from the measurement analysis we mapped this output to integer and then DAC INL, DNL analysis.
From the table of analysis section we found values for INL, DNL which are zeros.
Next, we have done ADC histogram ramp analysis.
In order to do so, we need much smaller step. We set the time step value as 5.12µs
Then again we map to integer and have done DAC INL DNL.
After that we have analysed histogram.
For this we found values for INL, DNL which are also zeros.
The resultant graphs are shown below:
Figure 04: Mapped to Interger
Figure 05: INL and DNL for Ramp input
Figure 06: INL and DNL for smaller time step
Figure 07: Histogram for Ramp input
# Analysis of 4 Bit ADC and DAC using sine input
To get the output for sine input we've disabled pulse signal, which we have used for ramp analysis previously.
After getting the output from DAC we extract data from a raw file given in the webpage, same as before in the ramp analysis.
At first, we set the start, stop time and time step, which are 0, 655.36µs, 5.12µs respectively.
Then we browse 4bit_ADC_DAC_pipe.raw file.
We'll get a nice DAC output curve which is same as ideal.In each wave form all the codes are covered.
This curve is only for output not with the input, so in the
simulation we have to write .save V(vout).
After that, from the measurement analysis we mapped this output to integer from 0 to 15 and then ADC histogram test.
From the table of analysis section we found values for INL, DNL which are zeros.
Here we have got average INL and DNL values.
Then we have done FFT analysis from a FFT data processing file given.
First, we copied integer values from below of the graphs and paste in the Input data segment of new webpage.
Before clicking the option of generate charts of FFT, INL, DNL, SNR at first we have to select read positive integer data option.
Finally, we got the same output of DAC sine input and FFT in according to the output and Histogram INL,DNL.
From the graph we can see the INL is zero because of missing codes.
Now, we set bit number to 4 instead of 10 and generate charts and got the real INL DNL curve.
Signal to noise ratio is 25dB.
The resultant graphs are shown below:
Figure 08: DAC output for sine input
Figure 09: Histogram for sine input
Figure 10: FFT for sine input
Figure 11: Histogram INL, DNL for sine input
# Simulation of real 4-bit R2R DAC.
A R2R DAC LTspice schematic is in the webpage, so our first task was to include
the schematic with 4bit ADC DAC schematic diagram.
Digital input for the real DAC is from the ADC output which is connected.
As the original data converted output will be from R2R, so we ignore Vout
of DAC and enable Vout of R2R.
we have used sine signal as test purpose.
The resultant graph is shown below:
Figure 12: Real R2R DAC output for sine input
# Analysing DNL, INL, FFT and SNR of ADC DAC with real 4-bit R2R DAC using sine input signal.
To fill some error, we have changed resistor values.
we have modified highest order bit (Resistor R9) to 1.5K instead of 2k and 2nd highest order bit(Resistor R6) to 1.3 instead of 1K.
After running it we got big jump in the middle, so it's not the similar as the ideal one.
Again we've used the raw file for extracting raw data, and set set the start, stop time and time step, which are 0, 655.36µs, 5.12µs respectively.
Then we mapped to integer and copy from table down.
Now, we have used java script file for FFT analysis.
First, we have pasted integer datas in the Input data segment of FFT data processing file.
Then, we read positive integer data and Generate charts.
From generated graphs we can see some codes are missing and hermonics are shown.
INL, DNL graph shows negative values below -1 and errors are noticed.
Signal to noise ratio is 18dB.
So, we lost 1 bit.
The resultant graphs are shown below:
Figure 13: R2R DAC distorted output for sine input
Figure 14: FFT for R2R DAC distorted output
Figure 15: Histogram INL, DNL for R2R DAC distorted output
# Analysing DNL, INL and LSB of ADC DAC with real 4-bit R2R DAC using ramp input signal.
The DAC is already filled with some error by changing resistor values.
As we will do ramp test, we need to enable Pulse input and disable sine input.
After running, we have noticed several jumps throughout the time duration of vout of DAC, so step sizes are not identical now.
Then we analyse this output from given raw file.
This time we have changed step time to 40.96µs and run the 4bit_ADC_DAC_pipe raw file.
We have seen Extracted time data and mapped it to integer. DAC INL,DNL analysis gives the indication of jumps in INL and DNL.
The resultant graphs are shown below:
Figure 16: Real R2R DAC distorted output for ramp input
Figure 17: INL, DNL for R2R DAC distorted output
# Data extraction from LTSpice by executing .MEAS script.
For measuring data I've prepared a measurment script file and execute it in LTspice.
.Measure TRAN V0000 FINDV(Vout) AT= 20u
.Measure TRAN V0001 FINDV(Vout) AT= 60u
.Measure TRAN V0002 FINDV(Vout) AT= 100u
.Measure TRAN V0003 FINDV(Vout) AT= 140u
.Measure TRAN V0004 FINDV(Vout) AT= 180u
.Measure TRAN V0005 FINDV(Vout) AT= 220u
.Measure TRAN V0006 FINDV(Vout) AT= 260u
.Measure TRAN V0007 FINDV(Vout) AT= 300u
.Measure TRAN V0008 FINDV(Vout) AT= 340u
.Measure TRAN V0009 FINDV(Vout) AT= 380u
.Measure TRAN V0010 FINDV(Vout) AT= 420u
.Measure TRAN V0011 FINDV(Vout) AT= 460u
.Measure TRAN V0012 FINDV(Vout) AT= 500u
.Measure TRAN V0013 FINDV(Vout) AT= 540u
.Measure TRAN V0014 FINDV(Vout) AT= 580u
.Measure TRAN V0015 FINDV(Vout) AT= 620u
The results are shown below:
* E:\IFE\Lab-3\web_Template\web_Template\InEl_P2019\2020_GroupA06_3_Rahman\LTSPICE\DAC_measure.mout
V0000: V(Vout)=0 at 2e-005
V0001: V(Vout)=0.0488599 at 6e-005
V0002: V(Vout)=0.0977199 at 0.0001
V0003: V(Vout)=0.14658 at 0.00014
V0004: V(Vout)=0.224756 at 0.00018
V0005: V(Vout)=0.273616 at 0.00022
V0006: V(Vout)=0.322476 at 0.00026
V0007: V(Vout)=0.371336 at 0.0003
V0008: V(Vout)=0.579805 at 0.00034
V0009: V(Vout)=0.628664 at 0.00038
V0010: V(Vout)=0.677524 at 0.00042
V0011: V(Vout)=0.726384 at 0.00046
V0012: V(Vout)=0.80456 at 0.0005
V0013: V(Vout)=0.85342 at 0.00054
V0014: V(Vout)=0.90228 at 0.00058
V0015: V(Vout)=0.95114 at 0.00062
# Lab Experience
- Could not figure out how to extract data only for V(out). Everytime I was getting diffrent curve at the raw file, just for considering both Vin and Vout.
- Tried to align graphs on the web page with but have got much more difficulties. It tooks so many times.
- Had difficulties with measurement script but found problems later on.
- Other tasks I found very easy, though due to not having much knowledge I could not write much about analysing.
# References
[1] https://personalpages.hs-kempten.de/~vollratj/InEl/2019_V03_ADC_DAC_Analysis.html
[2] https://personalpages.hs-kempten.de/~vollratj/InEl/Vollrath_InEl.html
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