Hochschule Kempten      
Fakultšt Elektrotechnik      
Microelectronics       Fachgebiet Elektronik, Prof. Vollrath      


Open Laboratory 2021: Cell optimization

Joerg Vollrath

Laboratory Instructions


In this laboratory cells from sclib.jelib are optimized and characterized.

Nr Matrikelnummer,
Name
Cell (sclib)
1*****916, ALUT22
2*****430, ALUT23
3*****708, ALUT24
4*****711, ALUT27
5*****407, BLUT28
6*****399, HLUT2B
7*****729, KLUT2D
8*****215, KLUT2E
9*****461, ÷LUT22
10*****414, RLUT23
11*****995, RLUT24
12*****727, RLUT27
13*****104, SLUT28
14*****305, SLUT2B
15*****443, TLUT2D
16*****807, ALUT2E
Cell and difficulty:
Normal (13): AND2, BUFGP, IBUF, LUT2B, LUT2D, LUT2E, LUT22, LUT23, LUT24, LUT27, LUT28, NAND2, OR2
Difficult (9): LUT2A, LUT2C, LUT26, LUT29, MUX2, MUX2D, MUX2L, MUXCY, XOR
More Difficult (5): MUX4, MUX4D, MUX4L, MUXF5=MUXF6=MUXF7, XORCY
Easy (6): LUT2F, LUT20, LUT25, MUX, OBUF, TG

Cell Layout Optimization


Create a new library with the cell name.
Place the original cell in.
Place a driving and load inverter in the library.
Create an optimized cell.
Create a test cell.
Optimize the cell layout and compare old and new design.
Example: Optimized cells Switch2a.jelib LUT21 as pictured above

Optimization rules


Characterization


Characterize functionality (truth table), delay times and power consumption with realistic source and load of the old and new cell with and without parasitics.

Deliverables


Explanation what you changed and why.
DRC no errors.
NCC no errors.
Layout
Delay times.
Power consumption.

Document your laboratory in a pdf document with a name of <Year>_Cell_ <name>.pdf and a <CellName>_<Initials>.jelib and send it to joerg.vollrath@hs-kempten.de.
Submission is due xx.xx.2021.