Microelectronics
	Microelectronics deals with design, manufacturing and test of integrated transistor circuits. At the beginning emphasis was on integrating as many transistors as possible in a small area achieving high operating speeds (timing closure). Nowadays in 10 nm technologies manufacturing costs and mask costs are very high and millions of transistors are available. Focus has changed to identify applications where millions of chips are needed (mobile phones) and to be able to build and verify robust circuits with millions of transistors in a short time frame. Microelectronics maintained a steady 30% productivity gain every 2 years over the last 30 years. Semiconductor manufacturing is using roadmaps, data collection and analysis (Big Data), simulation, automation in software and hardware (Industry 4.0) and dedicated test strategies (Design for test) and verification to be successfull.

Strategies in microelectronics:

• Realize any solution and optimize later only when needed: Premature optimization is evil.
• Verify each step as soon as possible: Do simulations and manufacturing data measurement
• Use automation and avoid manual work: Manual work adds possible errors and takes fixed amount of time
• Expect 30% productivity increase every year
• Be right on time: Every year a new product generation is needed. Sometimes advanced products fail.
• Reuse circuits and analyze competitors.
• Any task can be divided into smaller tasks hierarchically until a solution is found.

This class presents typical software tools for circuit development and manufacturing processes. A typical chip development example is done in the laboratory.

Microprocessors are the highest volumne integrated circuits developed mostly by ARM and Intel having an ARM, Intel, MIPS or RISC architecture. Processors realized in VHDL are partially available, but there is no open chip design with scan cells. A MIPS design of harvey mudd college is the most advanced publicly available processor without scan cells.
Graphics processors are a lower volumne product made by Intel, AMD and NVidia.
Microcontrollers are nice mixed signal designs based on ARM processors and availbale from many manufacturers.
Power integrated circuits and discrete devices are important for renewable energies and e-mobility.
A microcontroller as a data logger and electronic laboratory could be a mixed signal target device for this lecture.
Pure digital circuits can nowadays be realized in an FPGA and high level languages such as System C, Matlab Simulink or Labview can be used.
It would be nice to have these tools:
A JavaScript (language subset) to hardware compiler.
An AOI Schematic to standard cell layout tool for a single schematic cell.
Place and route with more than 2 metal layers.
LTSPICE simulation break up into smaller pieces with delay extraction.

Lecture

21.03.2023, 21.3.2023

1. Introduction:

Microelectronics, background, course content,
companies, references
Electrical simulation (LTSPICE): LTSPICE
Design and layout: Electric VLSI design system

Reading:
Video Introduction 17.03.2021
Video Laboratory start 22.03.2021

28.03.2023

2. Microelectronics History

Transistor evolution, history, Moore's law,
MOSFET transistor to chip

Reading:
Video Moore, Hierarchy, Inverter 24.03.2021

28.03.2023

3. MOSFET

Technologies and Systems
MOSFET: IV curves, static equation, layout and cross section

Laboratoy 1/2: Design and simulation of 1 μm and 50 nm CMOS transistors

Reading:
Video MOSFET 31.03.2021

4.04.2023

4. MOSFET Inverter:

MOSFET as capacitor, MOSFET switch model(R, C),
Inverter, IV curve, propagation delay, Standard cell, pass gate (PG), transmission gate (TG)

Laboratoy 1/2: Design and simulation of 1μm and 50 nm CMOS transistors

Reading:
Video Inverter 14.04.2021

18.04.2023

5. IC Manufacturing:

Wafer, chips
Yield, fabrication process, top view, cross section

Laboratoy 3/4: A CMOS inverter

Reading:
Video Process 19.04.2021

25.04.2023

6. Design rules and alignment

Schematic, layout and stick diagram

Laboratoy 3/4: A CMOS inverter



Reading:
Video Design Rules 28.04.2021

2.05.2023

7. RLC in microelectronics

NAND gate: parasitic resistance and capacitance, RCX extraction From logic gate layout to chip layout,
AOI (AND, OR, INVERT) design style,

Laboratory: Design of a PWM generator

Reading:
Video RLC and CMOS Logic 5.05.2021

4.05.2022
Laboratory 3/4: A CMOS inverter

Video Silicon Compiler 10.05.2021

09.05.2023

8. Silicon Compiler: From VHDL to layout

Unit Transistor,
Cell layout,
System synthesis,
VHDL entity and architecture
Synthesis and silicon compiler
VHDL hardware definition language
Entity, architecture, ports, busses, signals, hierarchy, state machine, test

12.05.2021 Video Truth table design style, VHDL

Reading:
17.05.2021 Video Laboratory Multiplier

16.05.2023

9. FPGA, VHDL and delay

ASIC, FPGA
Delay and pipeline operation

Reading:
Video Delay and power 2.06.2021
Video Laboratory Multiplier 31.05.2021

23.05.2023

10. Microelectronics system design

D-Flip-Flop, state machine and scan FF

Reading:
D-Flip-Flop, state machine 9.06.2021

Video Laboratory Multiplier 7.06.2021

06.06.2023

11. Memories

SRAM, DRAM, Flash
Example:Samsung 21nm, 48LV, 3 Bit per cell, 256Gb NAND Flash

Reading:
Video Memories 16.6.2021

Video Laboratoray 14.06.2021

13.06.2023

12. Power

Package,
Input outputs,
Clock


Reading:
Video Power, vdd, clock and input outputs 19.05.2020

Notes about laboratory 20.05.2020

20.06.2023

13. Design for test

Defects
Challenges of microelectronics
Review

27.05.2020 Laboratory: Progress and Questions

Reading:
Video Design for test, faults, test 26.05.2020

27.6.2023 04.07.2023

14. Review

Example exam

Laboratory: Design of a PWM

Reading:

Videos 2020

Questions

Laboratory 2023: Build a PWM generator
Laboratory 1/2 : Design and simulation of 1 µm and 50 nm CMOS transistors Example: Documentation format Report submission until 25.04.2023 Laboratory 3/4: A CMOS inverter Open Laboratory 5: Build a PWM generator Input and output signals Input: CLK, WE, D0..Di, EN Output: PWM Include a clock generator Make a schematic, layout and simulation Make a data sheet

Challenges Laboratory SS2023

Group work with large groups

• Dealing with very different knowledge
• Each person should be active and all persons should accomplish a result
• Personal results, learning and teaching portfolio
• Limited time for each student
• Limited number of pages (30) for grading to read for the professor
• One page per person (First 2 labs)
• How many results, learning and teaching accomplished? Report one in detail
• Can everybody of a large group report in detail something different?

Laboratory 2022: Compare full adders in various technologies

Open Laboratory 5: Build a full adder in a technology 1um..14nm and measure performance Goal is to verifiy the results of the papers: Analysis and Comparison on Full Adder Block in Submicron Technology, M. Alioto; G. Palumbo Compare_Full_Adder.pdf Two New Low Power High Performance Full Adders with Minimum Gates Journal of Computers 2009 v4-10-100_Full_adder_minimum_transistors.pdf and investigate technology changes 1um..14nm. Each group takes one architecture, does a layout and simulation with a certain technology and compares results.

Laboratory 2021: Build a 4 bit positive number multiplier

• Laboratory: Optimize and simulate a library cell
• Laboratory: Build a positive number 4 bit multiplier
  17.05.2021 Video Laboratory Multiplier
  
• Input: A 4 bit, B 4 bit
• Ouput Register with Scan function: C 8 bit
• Using 2 input LUTs and Multiplexers.
• Using adders
• Using custom circuits
• Using VHDL and synthesis
• Putting everything in a chip frame

Laboratory 2020: Build a 16 bit shift register converting gray code to binary code

Laboratory 5: Build a 16 bit shift register converting gray code to binary Inputs C3, C3b initiate a new serial parallel conversion C1, C1b, C2, C2b control a shift by one position of the input MSB comes first, LSB comes in last. Gray code to binary An EXOR operating with the previous bit converts gray to binary Outputs D0 to D15 are the final values of the parallel output Open Laboratory 6: Optimize and simulate a library cell SGrayBinary.vhdl FDC.jelib Laboratory Feedback

Problems:

Tools and Files

• Electric VLSI System
  Copy with Portable Java
• LTSPICE
  Copy LTSPICE IV
• Xilinx ISE Webpack 14
• Transfer Xilinx ISE Webpack Synthesis VHDL to Electric VHDL AnalyzeJS
• Generate LTSPICE and IRSIM waveforms from state tables TestJS
• Display electric layout and stick diagram on web pages (jelib.js) Test_HTML_jelib.html

• Transistor model: cmosedu_models.txt
• Library for VHDL synthesis: sclib.jelib
• Standard cell library available muddlib07.jelib
• Opamp: opamp.jelib
• Pads: pads4u.jelib
• MIPS processor: chip.arr
  cop0.jelib
  DatapathDone.jelib
  HMCLogosz.jelib
  Logo.jelib
  Logo_names.jelib
  Logosz.jelib
  memsys_final.jelib
  MIPS.jelib
  muddlib07.jelib
  muddpads13_ami05.jelib
  new_controller.jelib
  wordlib.jelib
  

1. Electric: http://www.staticfreesoft.com/index.html
2. CMOS Circuit Design and Layout: http://www.cmosedu.com/
3. LTSPICE: http://www.linear.com/designtools/software/
4. VLSI Design System Free Libraries http://www.staticfreesoft.com/productsLibraries.html

Past and Future Laboratories

• 2010 Rotary Encoder
  (1,2) Baker Electric Training, (3) LED control circuit, (4,5) AOI circuit, (6) Finite state machine, (7) counter design, (8) Pulse width modulator, (9) VHDL code, (10) Microcontroller
• 2011 Microprocessor
  (1,2) Electric Layout, (3,4) CMOS inverter, (5) Parasitics and Variations, (6-9) Adder in CMOS logic, (10) Adder in VHDL, (11,12) GNOME in VHDL
• 2012 Scan cell
  (1,2) Electric Layout, (3,4) CMOS inverter, (5) parasitics and variations, (6-12) Design of a scan cell
• 2013 Synthesis of a UART
  Synthesis of a UART from VHDL to Chip
• 2014 Pipeline ADC Chip
(5) Amplifiers and sample and Hold, (6) Design of a pipeline ADC stage
• 2015 Synthesis of a dynamic scan cell
• 2016 Build a mod_10_counter with minimum size transistors
  Instructions
• 2017 Build a 4 bit ALU
  Instructions
• 2018 Build a Tiny FPGA: Emphasis on Hardware Design
  Build an FPGA
• Synthesis of a MIPS processor
• Realization of a built in self test (BIST)
• Design of integrated CMOS amplifiers
• Design of a bigger FPGA

References: