Laboratory 2026: FPU investigation

• Laboratory 1/2 : Design and simulation of 1 µm and 50 nm CMOS transistors
  Example: Documentation format
  Report submission until xx.xx.2026
• Laboratory 3/4: A CMOS inverter Report submission until xx.xx.2026
• Floating point unit investigation
  https://en.wikipedia.org/wiki/Floating-point_arithmetic
• Floating point format options in this laboratory:
  8-Bit: 1 Bit Sign, 4 Bit significand, 3 Bit exponent
  FP8 (E4M3): 8-Bit: 1 Bit Sign, 3 Bit significand, 4 Bit exponent
  FP8 (E5M2): 8-Bit: 1 Bit Sign, 5 Bit significand, 2 Bit exponent
  7-Bit: 1 Bit Sign, 3 Bit significand, 3 Bit exponent
  7-Bit: 1 Bit Sign, 4 Bit significand, 2 Bit exponent
  FP6(E3M2): 6-Bit: 1 Bit Sign, 3 Bit significand, 2 Bit exponent
• Range calculation, fixed point floating point conversion
• Implementing operations: Add, subtract, multiply, divide, compare
  Description, VHDL, subcircuit schematic
• Design of scalable subcircuits
  Add with sign, multiply, genenrate 1 over significand, significand alignment, compare

Laboratory 2025: Serial CPU investigation

• Laboratory 1/2 : Design and simulation of 1 µm and 50 nm CMOS transistors
  Example: Documentation format
  Report submission until xx.xx.2025
• Laboratory 3/4: A CMOS inverter Report submission until 25.05.2025
• Serial processor investigation
• Synthesize a verilog description?
• Simulate the verilog description and the layout
• Investigate the layout
• Report submission until 06.07.2025

Laboratory 2024: Investigate Transistor Models

• Laboratory 1/2 : Design and simulation of 1 µm and 50 nm CMOS transistors
  Example: Documentation format
  Report submission until 25.04.2024
• Laboratory 3/4: A CMOS inverter Report submission until 26.05.2024
• Open Laboratory 5: Investigate Transistor models and performance
  
• Look for transistor IV-curves and associated models:
  Electronic Device Meeting, Solid state circuits
• Simulate inverter IV curves and delays and compare to literature
• Investigate minimum delay and transitor size optimization for load variations
• Discuss optimum performance

Laboratory 2023: Build a PWM generator

• Laboratory 1/2 : Design and simulation of 1 µm and 50 nm CMOS transistors
  Example: Documentation format
  Report submission until 25.04.2023
• Laboratory 3/4: A CMOS inverter
• Open Laboratory 5: Build a PWM generator
  
• Input and output signals
  Input: CLK, WE, D0..Di, EN Output: PWM
• Include a clock generator
• Make a schematic, layout and simulation
• Make a data sheet

Laboratory 2022: Compare full adders in various technologies

• Open Laboratory 5: Build a full adder in a technology 1um..14nm and measure performance
  

Laboratory 2020: Build a 16 bit shift register converting gray code to binary code

• Inputs
• C3, C3b initiate a new serial parallel conversion
• C1, C1b, C2, C2b control a shift by one position of the input
• MSB comes first, LSB comes in last.
• Gray code to binary
• An EXOR operating with the previous bit converts gray to binary
• Outputs
• D0 to D15 are the final values of the parallel output