Laboratory 2024: Investigate Transistor Models

• Laboratory 1/2 : Design and simulation of 1 µm and 50 nm CMOS transistors
  Example: Documentation format
  Report submission until 25.04.2023
• Laboratory 3/4: A CMOS inverter
• Open Laboratory 5: Investigate Transistor models and performance
  
• Look for transistor IV-curves and associated models:
  Electronic Device Meeting, Solid state circuits
• Simulate inverter IV curves and delays and compare to literature
• Investigate minimum delay and transitor size optimization for load variations
• Open :
  Measure IV-curves and compare to simulation
  Compare delays to IRSIM results

Laboratory 2023: Build a PWM generator
Laboratory 1/2 : Design and simulation of 1 µm and 50 nm CMOS transistors Example: Documentation format Report submission until 25.04.2023 Laboratory 3/4: A CMOS inverter Open Laboratory 5: Build a PWM generator Input and output signals Input: CLK, WE, D0..Di, EN Output: PWM Include a clock generator Make a schematic, layout and simulation Make a data sheet

Challenges Laboratory SS2023

Group work with large groups

• Dealing with very different knowledge
• Each person should be active and all persons should accomplish a result
• Personal results, learning and teaching portfolio
• Limited time for each student
• Limited number of pages (30) for grading to read for the professor
• One page per person (First 2 labs)
• How many results, learning and teaching accomplished? Report one in detail
• Can everybody of a large group report in detail something different?

Laboratory 2022: Compare full adders in various technologies

Open Laboratory 5: Build a full adder in a technology 1um..14nm and measure performance Goal is to verifiy the results of the papers: Analysis and Comparison on Full Adder Block in Submicron Technology, M. Alioto; G. Palumbo Compare_Full_Adder.pdf Two New Low Power High Performance Full Adders with Minimum Gates Journal of Computers 2009 v4-10-100_Full_adder_minimum_transistors.pdf and investigate technology changes 1um..14nm. Each group takes one architecture, does a layout and simulation with a certain technology and compares results.

Laboratory 2021: Build a 4 bit positive number multiplier

• Laboratory: Optimize and simulate a library cell
• Laboratory: Build a positive number 4 bit multiplier
  17.05.2021 Video Laboratory Multiplier
  
• Input: A 4 bit, B 4 bit
• Ouput Register with Scan function: C 8 bit
• Using 2 input LUTs and Multiplexers.
• Using adders
• Using custom circuits
• Using VHDL and synthesis
• Putting everything in a chip frame

Laboratory 2020: Build a 16 bit shift register converting gray code to binary code

Laboratory 5: Build a 16 bit shift register converting gray code to binary Inputs C3, C3b initiate a new serial parallel conversion C1, C1b, C2, C2b control a shift by one position of the input MSB comes first, LSB comes in last. Gray code to binary An EXOR operating with the previous bit converts gray to binary Outputs D0 to D15 are the final values of the parallel output Open Laboratory 6: Optimize and simulate a library cell SGrayBinary.vhdl FDC.jelib Laboratory Feedback

Problems:

Tools and Files

• Electric VLSI System
  Copy with Portable Java
• LTSPICE
  Copy LTSPICE IV
• Xilinx ISE Webpack 14
• Transfer Xilinx ISE Webpack Synthesis VHDL to Electric VHDL AnalyzeJS
• Generate LTSPICE and IRSIM waveforms from state tables TestJS
• Display electric layout and stick diagram on web pages (jelib.js) Test_HTML_jelib.html

• Transistor model: cmosedu_models.txt
• Library for VHDL synthesis: sclib.jelib
• Standard cell library available muddlib07.jelib
• Opamp: opamp.jelib
• Pads: pads4u.jelib
• MIPS processor: chip.arr
  cop0.jelib
  DatapathDone.jelib
  HMCLogosz.jelib
  Logo.jelib
  Logo_names.jelib
  Logosz.jelib
  memsys_final.jelib
  MIPS.jelib
  muddlib07.jelib
  muddpads13_ami05.jelib
  new_controller.jelib
  wordlib.jelib
  

1. Electric: http://www.staticfreesoft.com/index.html
2. CMOS Circuit Design and Layout: http://www.cmosedu.com/
3. LTSPICE: http://www.linear.com/designtools/software/
4. VLSI Design System Free Libraries http://www.staticfreesoft.com/productsLibraries.html

Past and Future Laboratories

• 2010 Rotary Encoder
  (1,2) Baker Electric Training, (3) LED control circuit, (4,5) AOI circuit, (6) Finite state machine, (7) counter design, (8) Pulse width modulator, (9) VHDL code, (10) Microcontroller
• 2011 Microprocessor
  (1,2) Electric Layout, (3,4) CMOS inverter, (5) Parasitics and Variations, (6-9) Adder in CMOS logic, (10) Adder in VHDL, (11,12) GNOME in VHDL
• 2012 Scan cell
  (1,2) Electric Layout, (3,4) CMOS inverter, (5) parasitics and variations, (6-12) Design of a scan cell
• 2013 Synthesis of a UART
  Synthesis of a UART from VHDL to Chip
• 2014 Pipeline ADC Chip
(5) Amplifiers and sample and Hold, (6) Design of a pipeline ADC stage
• 2015 Synthesis of a dynamic scan cell
• 2016 Build a mod_10_counter with minimum size transistors
  Instructions
• 2017 Build a 4 bit ALU
  Instructions
• 2018 Build a Tiny FPGA: Emphasis on Hardware Design
  Build an FPGA
• Synthesis of a MIPS processor
• Realization of a built in self test (BIST)
• Design of integrated CMOS amplifiers
• Design of a bigger FPGA

References: