Conversion Tool Xilinx ISE VHDL to Electric VHDL for SynthesisSince Electric:
Xilinx Webpack output should be for Spartan 6 devices and primitives. ToDo: Vivado primitives for Spartan 7. Setting of signals to '0' or '1'. Please check that all used functions are listed in the componnent section. Please remove the last semicolon at the end of the entity ports. Please copy the components between architecture and signals. This web page contains a UART example embedded in the webpage. |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use ALL;
use UNISIM.VPKG.ALL;
entity uart_test is
port (
clk : in STD_LOGIC := 'X';
reset : in STD_LOGIC := 'X';
rx : in STD_LOGIC := 'X';
tx : out STD_LOGIC;
an : out STD_LOGIC_VECTOR ( 3 downto 0 );
sseg : out STD_LOGIC_VECTOR ( 7 downto 0 );
led : out STD_LOGIC_VECTOR ( 7 downto 0 );
btn : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
end uart_test;
architecture Structure of uart_test is
signal Madd_rec_data1_xor_7_11 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N100 : STD_LOGIC;
signal N102 : STD_LOGIC;
signal N103 : STD_LOGIC;
signal N105 : STD_LOGIC;
signal N106 : STD_LOGIC;
signal N109 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N120 : STD_LOGIC;
signal N122 : STD_LOGIC;
signal N128 : STD_LOGIC;
signal N130 : STD_LOGIC;
signal N136 : STD_LOGIC;
signal N137 : STD_LOGIC;
signal N138 : STD_LOGIC;
signal N139 : STD_LOGIC;
signal N140 : STD_LOGIC;
signal N141 : STD_LOGIC;
signal N142 : STD_LOGIC;
signal N143 : STD_LOGIC;
signal N144 : STD_LOGIC;
signal N145 : STD_LOGIC;
signal N146 : STD_LOGIC;
signal N147 : STD_LOGIC;
signal N148 : STD_LOGIC;
signal N149 : STD_LOGIC;
signal N150 : STD_LOGIC;
signal N151 : STD_LOGIC;
signal N152 : STD_LOGIC;
signal N153 : STD_LOGIC;
signal N154 : STD_LOGIC;
signal N155 : STD_LOGIC;
signal N156 : STD_LOGIC;
signal N157 : STD_LOGIC;
signal N158 : STD_LOGIC;
signal N159 : STD_LOGIC;
signal N20 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal N23 : STD_LOGIC;
signal N25 : STD_LOGIC;
signal N27 : STD_LOGIC;
signal N29 : STD_LOGIC;
signal N31 : STD_LOGIC;
signal N33 : STD_LOGIC;
signal N35 : STD_LOGIC;
signal N37 : STD_LOGIC;
signal N39 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N40 : STD_LOGIC;
signal N42 : STD_LOGIC;
signal N44 : STD_LOGIC;
signal N46 : STD_LOGIC;
signal N47 : STD_LOGIC;
signal N49 : STD_LOGIC;
signal N52 : STD_LOGIC;
signal N55 : STD_LOGIC;
signal N56 : STD_LOGIC;
signal N66 : STD_LOGIC;
signal N68 : STD_LOGIC;
signal N70 : STD_LOGIC;
signal N72 : STD_LOGIC;
signal N74 : STD_LOGIC;
signal N76 : STD_LOGIC;
signal N78 : STD_LOGIC;
signal N79 : STD_LOGIC;
signal N81 : STD_LOGIC;
signal N82 : STD_LOGIC;
signal N84 : STD_LOGIC;
signal N86 : STD_LOGIC;
signal N88 : STD_LOGIC;
signal N90 : STD_LOGIC;
signal N91 : STD_LOGIC;
signal N93 : STD_LOGIC;
signal N94 : STD_LOGIC;
signal N96 : STD_LOGIC;
signal N97 : STD_LOGIC;
signal N99 : STD_LOGIC;
signal an_0_OBUF_90 : STD_LOGIC;
signal btn_0_IBUF_92 : STD_LOGIC;
signal btn_db_unit_Msub_q_next_share0000_cy_0_rt_94 : STD_LOGIC;
signal btn_db_unit_N01 : STD_LOGIC;
signal btn_db_unit_N11 : STD_LOGIC;
signal btn_db_unit_state_reg_FSM_FFd1_199 : STD_LOGIC;
signal btn_db_unit_state_reg_FSM_FFd1_In : STD_LOGIC;
signal btn_db_unit_state_reg_FSM_FFd1_1_201 : STD_LOGIC;
signal btn_db_unit_state_reg_FSM_FFd2_202 : STD_LOGIC;
signal btn_db_unit_state_reg_cmp_eq0000 : STD_LOGIC;
signal clk_BUFGP_216 : STD_LOGIC;
signal reset_IBUF_234 : STD_LOGIC;
signal rx_IBUF_236 : STD_LOGIC;
signal sseg_0_OBUF_245 : STD_LOGIC;
signal sseg_3_OBUF_246 : STD_LOGIC;
signal sseg_6_OBUF_247 : STD_LOGIC;
signal uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_3_Q : STD_LOGIC;
signal uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_5_Q : STD_LOGIC;
signal uart_unit_baud_gen_unit_r_next_cmp_eq000010_259 : STD_LOGIC;
signal uart_unit_baud_gen_unit_r_next_cmp_eq000022_260 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_3_269 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_31_270 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_32_271 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_33_272 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_34_273 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_35_274 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_36_275 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_37_276 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_4_277 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_41_278 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_42_279 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_43_280 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_44_281 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_45_282 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_46_283 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_Mmux_r_data_47_284 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_N01 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_0_286 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_1_287 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_2_288 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_3_289 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_4_290 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_5_291 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_6_292 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_7_293 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_0_and0000 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_0_295 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_1_296 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_2_297 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_3_298 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_4_299 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_5_300 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_6_301 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_7_302 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_1_and0000 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_0_304 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_1_305 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_2_306 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_3_307 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_4_308 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_5_309 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_6_310 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_7_311 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_2_and0000 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_0_313 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_1_314 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_2_315 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_3_316 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_4_317 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_5_318 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_6_319 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_7_320 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_array_reg_3_and0000 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_empty_reg_322 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_empty_reg_mux0000 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_full_reg_324 : STD_LOGIC;
signal uart_unit_fifo_rx_unit_full_reg_mux0000 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_3_334 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_31_335 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_32_336 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_33_337 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_34_338 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_35_339 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_36_340 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_37_341 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_4_342 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_41_343 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_42_344 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_43_345 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_44_346 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_45_347 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_46_348 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_Mmux_r_data_47_349 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_N01 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_0_351 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_1_352 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_2_353 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_3_354 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_4_355 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_5_356 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_6_357 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_7_358 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_0_and0000 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_0_360 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_1_361 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_2_362 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_3_363 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_4_364 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_5_365 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_6_366 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_7_367 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_1_and0000 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_0_369 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_1_370 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_2_371 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_3_372 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_4_373 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_5_374 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_6_375 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_7_376 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_2_and0000 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_0_378 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_1_379 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_2_380 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_3_381 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_4_382 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_5_383 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_6_384 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_7_385 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_array_reg_3_and0000 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_empty_reg_387 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_empty_reg_mux0000 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_full_reg_389 : STD_LOGIC;
signal uart_unit_fifo_tx_unit_full_reg_mux0000 : STD_LOGIC;
signal uart_unit_rx_done_tick : STD_LOGIC;
signal uart_unit_tick : STD_LOGIC;
signal uart_unit_tx_done_tick : STD_LOGIC;
signal uart_unit_uart_rx_unit_N01 : STD_LOGIC;
signal uart_unit_uart_rx_unit_N15 : STD_LOGIC;
signal uart_unit_uart_rx_unit_N16 : STD_LOGIC;
signal uart_unit_uart_rx_unit_N21 : STD_LOGIC;
signal uart_unit_uart_rx_unit_N6 : STD_LOGIC;
signal uart_unit_uart_rx_unit_b_reg_not0001 : STD_LOGIC;
signal uart_unit_uart_rx_unit_n_reg_mux0000_2_18_430 : STD_LOGIC;
signal uart_unit_uart_rx_unit_n_reg_mux0000_2_8_431 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_0_21_437 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_0_31_438 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_0_7 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_2_16_442 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_2_44_443 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_2_51_444 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_2_8_445 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_3_14_447 : STD_LOGIC;
signal uart_unit_uart_rx_unit_s_reg_mux0000_3_6_448 : STD_LOGIC;
signal uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449 : STD_LOGIC;
signal uart_unit_uart_rx_unit_state_reg_FSM_FFd1_In_450 : STD_LOGIC;
signal uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451 : STD_LOGIC;
signal uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In : STD_LOGIC;
signal uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In12_453 : STD_LOGIC;
signal uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In35_454 : STD_LOGIC;
signal uart_unit_uart_rx_unit_state_reg_cmp_eq0001 : STD_LOGIC;
signal uart_unit_uart_tx_unit_N01 : STD_LOGIC;
signal uart_unit_uart_tx_unit_N2 : STD_LOGIC;
signal uart_unit_uart_tx_unit_N3 : STD_LOGIC;
signal uart_unit_uart_tx_unit_N6 : STD_LOGIC;
signal uart_unit_uart_tx_unit_N7 : STD_LOGIC;
signal uart_unit_uart_tx_unit_n_reg_mux0000_0_1_481 : STD_LOGIC;
signal uart_unit_uart_tx_unit_n_reg_mux0000_0_2_482 : STD_LOGIC;
signal uart_unit_uart_tx_unit_n_reg_mux0000_1_1_484 : STD_LOGIC;
signal uart_unit_uart_tx_unit_n_reg_mux0000_1_2_485 : STD_LOGIC;
signal uart_unit_uart_tx_unit_n_reg_mux0000_2_1_487 : STD_LOGIC;
signal uart_unit_uart_tx_unit_n_reg_mux0000_2_2_488 : STD_LOGIC;
signal uart_unit_uart_tx_unit_s_reg_mux0000_0_34_494 : STD_LOGIC;
signal uart_unit_uart_tx_unit_s_reg_mux0000_0_37_495 : STD_LOGIC;
signal uart_unit_uart_tx_unit_s_reg_mux0000_1_27_497 : STD_LOGIC;
signal uart_unit_uart_tx_unit_s_reg_mux0000_2_19_499 : STD_LOGIC;
signal uart_unit_uart_tx_unit_s_reg_mux0000_2_68 : STD_LOGIC;
signal uart_unit_uart_tx_unit_s_reg_mux0000_2_681_501 : STD_LOGIC;
signal uart_unit_uart_tx_unit_s_reg_mux0000_2_8_502 : STD_LOGIC;
signal uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504 : STD_LOGIC;
signal uart_unit_uart_tx_unit_state_reg_FSM_FFd1_In : STD_LOGIC;
signal uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506 : STD_LOGIC;
signal uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In : STD_LOGIC;
signal uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In12_508 : STD_LOGIC;
signal uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In35_509 : STD_LOGIC;
signal uart_unit_uart_tx_unit_state_reg_cmp_eq0000 : STD_LOGIC;
signal uart_unit_uart_tx_unit_tx_next : STD_LOGIC;
signal uart_unit_uart_tx_unit_tx_reg_512 : STD_LOGIC;
signal Madd_rec_data1_cy : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Madd_rec_data1_lut : STD_LOGIC_VECTOR ( 7 downto 1 );
signal btn_db_unit_Msub_q_next_share0000_cy : STD_LOGIC_VECTOR ( 19 downto 0 );
signal btn_db_unit_Msub_q_next_share0000_lut : STD_LOGIC_VECTOR ( 20 downto 1 );
signal btn_db_unit_q_next : STD_LOGIC_VECTOR ( 20 downto 0 );
signal btn_db_unit_q_next_share0000 : STD_LOGIC_VECTOR ( 20 downto 0 );
signal btn_db_unit_q_reg : STD_LOGIC_VECTOR ( 20 downto 0 );
signal btn_db_unit_state_reg_cmp_eq0000_wg_cy : STD_LOGIC_VECTOR ( 4 downto 0 );
signal btn_db_unit_state_reg_cmp_eq0000_wg_lut : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rec_data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_unit_baud_gen_unit_r_next : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_unit_baud_gen_unit_r_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_unit_fifo_rx_unit_r_ptr_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_fifo_rx_unit_r_ptr_reg_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_fifo_rx_unit_w_ptr_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_fifo_rx_unit_w_ptr_reg_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_fifo_tx_unit_r_ptr_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_fifo_tx_unit_r_ptr_reg_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_fifo_tx_unit_w_ptr_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_fifo_tx_unit_w_ptr_reg_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal uart_unit_tx_fifo_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_unit_uart_rx_unit_b_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_unit_uart_rx_unit_n_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
signal uart_unit_uart_rx_unit_n_reg_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal uart_unit_uart_rx_unit_s_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
signal uart_unit_uart_rx_unit_s_reg_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal uart_unit_uart_tx_unit_b_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_unit_uart_tx_unit_b_reg_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_unit_uart_tx_unit_n_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
signal uart_unit_uart_tx_unit_n_reg_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal uart_unit_uart_tx_unit_s_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
signal uart_unit_uart_tx_unit_s_reg_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
XST_GND : GND
port map (
G => an_0_OBUF_90
);
XST_VCC : VCC
port map (
P => sseg_0_OBUF_245
);
btn_db_unit_state_reg_FSM_FFd2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_0_IBUF_92,
Q => btn_db_unit_state_reg_FSM_FFd2_202
);
btn_db_unit_state_reg_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_state_reg_FSM_FFd1_In,
Q => btn_db_unit_state_reg_FSM_FFd1_199
);
btn_db_unit_Msub_q_next_share0000_xor_20_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(19),
LI => btn_db_unit_Msub_q_next_share0000_lut(20),
O => btn_db_unit_q_next_share0000(20)
);
btn_db_unit_Msub_q_next_share0000_xor_19_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(18),
LI => btn_db_unit_Msub_q_next_share0000_lut(19),
O => btn_db_unit_q_next_share0000(19)
);
btn_db_unit_Msub_q_next_share0000_cy_19_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(18),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(19),
O => btn_db_unit_Msub_q_next_share0000_cy(19)
);
btn_db_unit_Msub_q_next_share0000_xor_18_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(17),
LI => btn_db_unit_Msub_q_next_share0000_lut(18),
O => btn_db_unit_q_next_share0000(18)
);
btn_db_unit_Msub_q_next_share0000_cy_18_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(17),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(18),
O => btn_db_unit_Msub_q_next_share0000_cy(18)
);
btn_db_unit_Msub_q_next_share0000_xor_17_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(16),
LI => btn_db_unit_Msub_q_next_share0000_lut(17),
O => btn_db_unit_q_next_share0000(17)
);
btn_db_unit_Msub_q_next_share0000_cy_17_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(16),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(17),
O => btn_db_unit_Msub_q_next_share0000_cy(17)
);
btn_db_unit_Msub_q_next_share0000_xor_16_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(15),
LI => btn_db_unit_Msub_q_next_share0000_lut(16),
O => btn_db_unit_q_next_share0000(16)
);
btn_db_unit_Msub_q_next_share0000_cy_16_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(15),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(16),
O => btn_db_unit_Msub_q_next_share0000_cy(16)
);
btn_db_unit_Msub_q_next_share0000_xor_15_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(14),
LI => btn_db_unit_Msub_q_next_share0000_lut(15),
O => btn_db_unit_q_next_share0000(15)
);
btn_db_unit_Msub_q_next_share0000_cy_15_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(14),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(15),
O => btn_db_unit_Msub_q_next_share0000_cy(15)
);
btn_db_unit_Msub_q_next_share0000_xor_14_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(13),
LI => btn_db_unit_Msub_q_next_share0000_lut(14),
O => btn_db_unit_q_next_share0000(14)
);
btn_db_unit_Msub_q_next_share0000_cy_14_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(13),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(14),
O => btn_db_unit_Msub_q_next_share0000_cy(14)
);
btn_db_unit_Msub_q_next_share0000_xor_13_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(12),
LI => btn_db_unit_Msub_q_next_share0000_lut(13),
O => btn_db_unit_q_next_share0000(13)
);
btn_db_unit_Msub_q_next_share0000_cy_13_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(12),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(13),
O => btn_db_unit_Msub_q_next_share0000_cy(13)
);
btn_db_unit_Msub_q_next_share0000_xor_12_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(11),
LI => btn_db_unit_Msub_q_next_share0000_lut(12),
O => btn_db_unit_q_next_share0000(12)
);
btn_db_unit_Msub_q_next_share0000_cy_12_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(11),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(12),
O => btn_db_unit_Msub_q_next_share0000_cy(12)
);
btn_db_unit_Msub_q_next_share0000_xor_11_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(10),
LI => btn_db_unit_Msub_q_next_share0000_lut(11),
O => btn_db_unit_q_next_share0000(11)
);
btn_db_unit_Msub_q_next_share0000_cy_11_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(10),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(11),
O => btn_db_unit_Msub_q_next_share0000_cy(11)
);
btn_db_unit_Msub_q_next_share0000_xor_10_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(9),
LI => btn_db_unit_Msub_q_next_share0000_lut(10),
O => btn_db_unit_q_next_share0000(10)
);
btn_db_unit_Msub_q_next_share0000_cy_10_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(9),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(10),
O => btn_db_unit_Msub_q_next_share0000_cy(10)
);
btn_db_unit_Msub_q_next_share0000_xor_9_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(8),
LI => btn_db_unit_Msub_q_next_share0000_lut(9),
O => btn_db_unit_q_next_share0000(9)
);
btn_db_unit_Msub_q_next_share0000_cy_9_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(8),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(9),
O => btn_db_unit_Msub_q_next_share0000_cy(9)
);
btn_db_unit_Msub_q_next_share0000_xor_8_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(7),
LI => btn_db_unit_Msub_q_next_share0000_lut(8),
O => btn_db_unit_q_next_share0000(8)
);
btn_db_unit_Msub_q_next_share0000_cy_8_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(7),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(8),
O => btn_db_unit_Msub_q_next_share0000_cy(8)
);
btn_db_unit_Msub_q_next_share0000_xor_7_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(6),
LI => btn_db_unit_Msub_q_next_share0000_lut(7),
O => btn_db_unit_q_next_share0000(7)
);
btn_db_unit_Msub_q_next_share0000_cy_7_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(6),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(7),
O => btn_db_unit_Msub_q_next_share0000_cy(7)
);
btn_db_unit_Msub_q_next_share0000_xor_6_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(5),
LI => btn_db_unit_Msub_q_next_share0000_lut(6),
O => btn_db_unit_q_next_share0000(6)
);
btn_db_unit_Msub_q_next_share0000_cy_6_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(5),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(6),
O => btn_db_unit_Msub_q_next_share0000_cy(6)
);
btn_db_unit_Msub_q_next_share0000_xor_5_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(4),
LI => btn_db_unit_Msub_q_next_share0000_lut(5),
O => btn_db_unit_q_next_share0000(5)
);
btn_db_unit_Msub_q_next_share0000_cy_5_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(4),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(5),
O => btn_db_unit_Msub_q_next_share0000_cy(5)
);
btn_db_unit_Msub_q_next_share0000_xor_4_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(3),
LI => btn_db_unit_Msub_q_next_share0000_lut(4),
O => btn_db_unit_q_next_share0000(4)
);
btn_db_unit_Msub_q_next_share0000_cy_4_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(3),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(4),
O => btn_db_unit_Msub_q_next_share0000_cy(4)
);
btn_db_unit_Msub_q_next_share0000_xor_3_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(2),
LI => btn_db_unit_Msub_q_next_share0000_lut(3),
O => btn_db_unit_q_next_share0000(3)
);
btn_db_unit_Msub_q_next_share0000_cy_3_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(2),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(3),
O => btn_db_unit_Msub_q_next_share0000_cy(3)
);
btn_db_unit_Msub_q_next_share0000_xor_2_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(1),
LI => btn_db_unit_Msub_q_next_share0000_lut(2),
O => btn_db_unit_q_next_share0000(2)
);
btn_db_unit_Msub_q_next_share0000_cy_2_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(1),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(2),
O => btn_db_unit_Msub_q_next_share0000_cy(2)
);
btn_db_unit_Msub_q_next_share0000_xor_1_Q : XORCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(0),
LI => btn_db_unit_Msub_q_next_share0000_lut(1),
O => btn_db_unit_q_next_share0000(1)
);
btn_db_unit_Msub_q_next_share0000_cy_1_Q : MUXCY
port map (
CI => btn_db_unit_Msub_q_next_share0000_cy(0),
DI => sseg_0_OBUF_245,
S => btn_db_unit_Msub_q_next_share0000_lut(1),
O => btn_db_unit_Msub_q_next_share0000_cy(1)
);
btn_db_unit_Msub_q_next_share0000_xor_0_Q : XORCY
port map (
CI => sseg_0_OBUF_245,
LI => btn_db_unit_Msub_q_next_share0000_cy_0_rt_94,
O => btn_db_unit_q_next_share0000(0)
);
btn_db_unit_Msub_q_next_share0000_cy_0_Q : MUXCY
port map (
CI => sseg_0_OBUF_245,
DI => an_0_OBUF_90,
S => btn_db_unit_Msub_q_next_share0000_cy_0_rt_94,
O => btn_db_unit_Msub_q_next_share0000_cy(0)
);
btn_db_unit_q_reg_20 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(20),
Q => btn_db_unit_q_reg(20)
);
btn_db_unit_q_reg_19 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(19),
Q => btn_db_unit_q_reg(19)
);
btn_db_unit_q_reg_18 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(18),
Q => btn_db_unit_q_reg(18)
);
btn_db_unit_q_reg_17 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(17),
Q => btn_db_unit_q_reg(17)
);
btn_db_unit_q_reg_16 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(16),
Q => btn_db_unit_q_reg(16)
);
btn_db_unit_q_reg_15 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(15),
Q => btn_db_unit_q_reg(15)
);
btn_db_unit_q_reg_14 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(14),
Q => btn_db_unit_q_reg(14)
);
btn_db_unit_q_reg_13 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(13),
Q => btn_db_unit_q_reg(13)
);
btn_db_unit_q_reg_12 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(12),
Q => btn_db_unit_q_reg(12)
);
btn_db_unit_q_reg_11 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(11),
Q => btn_db_unit_q_reg(11)
);
btn_db_unit_q_reg_10 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(10),
Q => btn_db_unit_q_reg(10)
);
btn_db_unit_q_reg_9 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(9),
Q => btn_db_unit_q_reg(9)
);
btn_db_unit_q_reg_8 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(8),
Q => btn_db_unit_q_reg(8)
);
btn_db_unit_q_reg_7 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(7),
Q => btn_db_unit_q_reg(7)
);
btn_db_unit_q_reg_6 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(6),
Q => btn_db_unit_q_reg(6)
);
btn_db_unit_q_reg_5 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(5),
Q => btn_db_unit_q_reg(5)
);
btn_db_unit_q_reg_4 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(4),
Q => btn_db_unit_q_reg(4)
);
btn_db_unit_q_reg_3 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(3),
Q => btn_db_unit_q_reg(3)
);
btn_db_unit_q_reg_2 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(2),
Q => btn_db_unit_q_reg(2)
);
btn_db_unit_q_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(1),
Q => btn_db_unit_q_reg(1)
);
btn_db_unit_q_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_q_next(0),
Q => btn_db_unit_q_reg(0)
);
uart_unit_baud_gen_unit_r_reg_7 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(7),
Q => uart_unit_baud_gen_unit_r_reg(7)
);
uart_unit_baud_gen_unit_r_reg_6 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(6),
Q => uart_unit_baud_gen_unit_r_reg(6)
);
uart_unit_baud_gen_unit_r_reg_5 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(5),
Q => uart_unit_baud_gen_unit_r_reg(5)
);
uart_unit_baud_gen_unit_r_reg_4 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(4),
Q => uart_unit_baud_gen_unit_r_reg(4)
);
uart_unit_baud_gen_unit_r_reg_3 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(3),
Q => uart_unit_baud_gen_unit_r_reg(3)
);
uart_unit_baud_gen_unit_r_reg_2 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(2),
Q => uart_unit_baud_gen_unit_r_reg(2)
);
uart_unit_baud_gen_unit_r_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(1),
Q => uart_unit_baud_gen_unit_r_reg(1)
);
uart_unit_baud_gen_unit_r_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_baud_gen_unit_r_next(0),
Q => uart_unit_baud_gen_unit_r_reg(0)
);
uart_unit_uart_rx_unit_state_reg_FSM_FFd2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In,
Q => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451
);
uart_unit_uart_rx_unit_state_reg_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_In_450,
Q => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449
);
uart_unit_uart_rx_unit_s_reg_3 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_s_reg_mux0000(0),
Q => uart_unit_uart_rx_unit_s_reg(3)
);
uart_unit_uart_rx_unit_s_reg_2 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_s_reg_mux0000(1),
Q => uart_unit_uart_rx_unit_s_reg(2)
);
uart_unit_uart_rx_unit_s_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_s_reg_mux0000(2),
Q => uart_unit_uart_rx_unit_s_reg(1)
);
uart_unit_uart_rx_unit_s_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_s_reg_mux0000(3),
Q => uart_unit_uart_rx_unit_s_reg(0)
);
uart_unit_uart_rx_unit_n_reg_2 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_n_reg_mux0000(2),
Q => uart_unit_uart_rx_unit_n_reg(2)
);
uart_unit_uart_rx_unit_n_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_n_reg_mux0000(1),
Q => uart_unit_uart_rx_unit_n_reg(1)
);
uart_unit_uart_rx_unit_n_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_n_reg_mux0000(0),
Q => uart_unit_uart_rx_unit_n_reg(0)
);
uart_unit_uart_rx_unit_b_reg_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => rx_IBUF_236,
Q => uart_unit_uart_rx_unit_b_reg(7)
);
uart_unit_uart_rx_unit_b_reg_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(7),
Q => uart_unit_uart_rx_unit_b_reg(6)
);
uart_unit_uart_rx_unit_b_reg_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(6),
Q => uart_unit_uart_rx_unit_b_reg(5)
);
uart_unit_uart_rx_unit_b_reg_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(5),
Q => uart_unit_uart_rx_unit_b_reg(4)
);
uart_unit_uart_rx_unit_b_reg_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(4),
Q => uart_unit_uart_rx_unit_b_reg(3)
);
uart_unit_uart_rx_unit_b_reg_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(3),
Q => uart_unit_uart_rx_unit_b_reg(2)
);
uart_unit_uart_rx_unit_b_reg_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(2),
Q => uart_unit_uart_rx_unit_b_reg(1)
);
uart_unit_uart_rx_unit_b_reg_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_uart_rx_unit_b_reg_not0001,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(1),
Q => uart_unit_uart_rx_unit_b_reg(0)
);
uart_unit_fifo_rx_unit_Mmux_r_data_3 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_0_304,
I2 => uart_unit_fifo_rx_unit_array_reg_3_0_313,
O => uart_unit_fifo_rx_unit_Mmux_r_data_3_269
);
uart_unit_fifo_rx_unit_Mmux_r_data_4 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_0_286,
I2 => uart_unit_fifo_rx_unit_array_reg_1_0_295,
O => uart_unit_fifo_rx_unit_Mmux_r_data_4_277
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_4_277,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_3_269,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_cy(0)
);
uart_unit_fifo_rx_unit_Mmux_r_data_31 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_1_305,
I2 => uart_unit_fifo_rx_unit_array_reg_3_1_314,
O => uart_unit_fifo_rx_unit_Mmux_r_data_31_270
);
uart_unit_fifo_rx_unit_Mmux_r_data_41 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_1_287,
I2 => uart_unit_fifo_rx_unit_array_reg_1_1_296,
O => uart_unit_fifo_rx_unit_Mmux_r_data_41_278
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5_0 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_41_278,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_31_270,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_lut(1)
);
uart_unit_fifo_rx_unit_Mmux_r_data_32 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_2_306,
I2 => uart_unit_fifo_rx_unit_array_reg_3_2_315,
O => uart_unit_fifo_rx_unit_Mmux_r_data_32_271
);
uart_unit_fifo_rx_unit_Mmux_r_data_42 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_2_288,
I2 => uart_unit_fifo_rx_unit_array_reg_1_2_297,
O => uart_unit_fifo_rx_unit_Mmux_r_data_42_279
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5_1 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_42_279,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_32_271,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_lut(2)
);
uart_unit_fifo_rx_unit_Mmux_r_data_33 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_3_307,
I2 => uart_unit_fifo_rx_unit_array_reg_3_3_316,
O => uart_unit_fifo_rx_unit_Mmux_r_data_33_272
);
uart_unit_fifo_rx_unit_Mmux_r_data_43 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_3_289,
I2 => uart_unit_fifo_rx_unit_array_reg_1_3_298,
O => uart_unit_fifo_rx_unit_Mmux_r_data_43_280
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5_2 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_43_280,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_33_272,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_lut(3)
);
uart_unit_fifo_rx_unit_Mmux_r_data_34 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_4_308,
I2 => uart_unit_fifo_rx_unit_array_reg_3_4_317,
O => uart_unit_fifo_rx_unit_Mmux_r_data_34_273
);
uart_unit_fifo_rx_unit_Mmux_r_data_44 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_4_290,
I2 => uart_unit_fifo_rx_unit_array_reg_1_4_299,
O => uart_unit_fifo_rx_unit_Mmux_r_data_44_281
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5_3 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_44_281,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_34_273,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_lut(4)
);
uart_unit_fifo_rx_unit_Mmux_r_data_35 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_5_309,
I2 => uart_unit_fifo_rx_unit_array_reg_3_5_318,
O => uart_unit_fifo_rx_unit_Mmux_r_data_35_274
);
uart_unit_fifo_rx_unit_Mmux_r_data_45 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_5_291,
I2 => uart_unit_fifo_rx_unit_array_reg_1_5_300,
O => uart_unit_fifo_rx_unit_Mmux_r_data_45_282
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5_4 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_45_282,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_35_274,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_lut(5)
);
uart_unit_fifo_rx_unit_Mmux_r_data_36 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_6_310,
I2 => uart_unit_fifo_rx_unit_array_reg_3_6_319,
O => uart_unit_fifo_rx_unit_Mmux_r_data_36_275
);
uart_unit_fifo_rx_unit_Mmux_r_data_46 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_6_292,
I2 => uart_unit_fifo_rx_unit_array_reg_1_6_301,
O => uart_unit_fifo_rx_unit_Mmux_r_data_46_283
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5_5 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_46_283,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_36_275,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_lut(6)
);
uart_unit_fifo_rx_unit_Mmux_r_data_37 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_2_7_311,
I2 => uart_unit_fifo_rx_unit_array_reg_3_7_320,
O => uart_unit_fifo_rx_unit_Mmux_r_data_37_276
);
uart_unit_fifo_rx_unit_Mmux_r_data_47 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_array_reg_0_7_293,
I2 => uart_unit_fifo_rx_unit_array_reg_1_7_302,
O => uart_unit_fifo_rx_unit_Mmux_r_data_47_284
);
uart_unit_fifo_rx_unit_Mmux_r_data_2_f5_6 : MUXF5
port map (
I0 => uart_unit_fifo_rx_unit_Mmux_r_data_47_284,
I1 => uart_unit_fifo_rx_unit_Mmux_r_data_37_276,
S => uart_unit_fifo_rx_unit_r_ptr_reg(1),
O => Madd_rec_data1_lut(7)
);
uart_unit_fifo_rx_unit_r_ptr_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_rx_unit_r_ptr_reg_mux0000(1),
Q => uart_unit_fifo_rx_unit_r_ptr_reg(1)
);
uart_unit_fifo_rx_unit_r_ptr_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_rx_unit_r_ptr_reg_mux0000(0),
Q => uart_unit_fifo_rx_unit_r_ptr_reg(0)
);
uart_unit_fifo_rx_unit_w_ptr_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_rx_unit_w_ptr_reg_mux0000(1),
Q => uart_unit_fifo_rx_unit_w_ptr_reg(1)
);
uart_unit_fifo_rx_unit_w_ptr_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_rx_unit_w_ptr_reg_mux0000(0),
Q => uart_unit_fifo_rx_unit_w_ptr_reg(0)
);
uart_unit_fifo_rx_unit_full_reg : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_rx_unit_full_reg_mux0000,
Q => uart_unit_fifo_rx_unit_full_reg_324
);
uart_unit_fifo_rx_unit_empty_reg : FDP
port map (
C => clk_BUFGP_216,
D => uart_unit_fifo_rx_unit_empty_reg_mux0000,
PRE => reset_IBUF_234,
Q => uart_unit_fifo_rx_unit_empty_reg_322
);
uart_unit_fifo_rx_unit_array_reg_3_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(7),
Q => uart_unit_fifo_rx_unit_array_reg_3_7_320
);
uart_unit_fifo_rx_unit_array_reg_3_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(6),
Q => uart_unit_fifo_rx_unit_array_reg_3_6_319
);
uart_unit_fifo_rx_unit_array_reg_3_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(5),
Q => uart_unit_fifo_rx_unit_array_reg_3_5_318
);
uart_unit_fifo_rx_unit_array_reg_3_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(4),
Q => uart_unit_fifo_rx_unit_array_reg_3_4_317
);
uart_unit_fifo_rx_unit_array_reg_3_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(3),
Q => uart_unit_fifo_rx_unit_array_reg_3_3_316
);
uart_unit_fifo_rx_unit_array_reg_3_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(2),
Q => uart_unit_fifo_rx_unit_array_reg_3_2_315
);
uart_unit_fifo_rx_unit_array_reg_3_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(1),
Q => uart_unit_fifo_rx_unit_array_reg_3_1_314
);
uart_unit_fifo_rx_unit_array_reg_3_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(0),
Q => uart_unit_fifo_rx_unit_array_reg_3_0_313
);
uart_unit_fifo_rx_unit_array_reg_1_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(7),
Q => uart_unit_fifo_rx_unit_array_reg_1_7_302
);
uart_unit_fifo_rx_unit_array_reg_1_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(6),
Q => uart_unit_fifo_rx_unit_array_reg_1_6_301
);
uart_unit_fifo_rx_unit_array_reg_1_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(5),
Q => uart_unit_fifo_rx_unit_array_reg_1_5_300
);
uart_unit_fifo_rx_unit_array_reg_1_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(4),
Q => uart_unit_fifo_rx_unit_array_reg_1_4_299
);
uart_unit_fifo_rx_unit_array_reg_1_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(3),
Q => uart_unit_fifo_rx_unit_array_reg_1_3_298
);
uart_unit_fifo_rx_unit_array_reg_1_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(2),
Q => uart_unit_fifo_rx_unit_array_reg_1_2_297
);
uart_unit_fifo_rx_unit_array_reg_1_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(1),
Q => uart_unit_fifo_rx_unit_array_reg_1_1_296
);
uart_unit_fifo_rx_unit_array_reg_1_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(0),
Q => uart_unit_fifo_rx_unit_array_reg_1_0_295
);
uart_unit_fifo_rx_unit_array_reg_0_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(7),
Q => uart_unit_fifo_rx_unit_array_reg_0_7_293
);
uart_unit_fifo_rx_unit_array_reg_0_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(6),
Q => uart_unit_fifo_rx_unit_array_reg_0_6_292
);
uart_unit_fifo_rx_unit_array_reg_0_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(5),
Q => uart_unit_fifo_rx_unit_array_reg_0_5_291
);
uart_unit_fifo_rx_unit_array_reg_0_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(4),
Q => uart_unit_fifo_rx_unit_array_reg_0_4_290
);
uart_unit_fifo_rx_unit_array_reg_0_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(3),
Q => uart_unit_fifo_rx_unit_array_reg_0_3_289
);
uart_unit_fifo_rx_unit_array_reg_0_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(2),
Q => uart_unit_fifo_rx_unit_array_reg_0_2_288
);
uart_unit_fifo_rx_unit_array_reg_0_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(1),
Q => uart_unit_fifo_rx_unit_array_reg_0_1_287
);
uart_unit_fifo_rx_unit_array_reg_0_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(0),
Q => uart_unit_fifo_rx_unit_array_reg_0_0_286
);
uart_unit_fifo_rx_unit_array_reg_2_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(7),
Q => uart_unit_fifo_rx_unit_array_reg_2_7_311
);
uart_unit_fifo_rx_unit_array_reg_2_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(6),
Q => uart_unit_fifo_rx_unit_array_reg_2_6_310
);
uart_unit_fifo_rx_unit_array_reg_2_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(5),
Q => uart_unit_fifo_rx_unit_array_reg_2_5_309
);
uart_unit_fifo_rx_unit_array_reg_2_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(4),
Q => uart_unit_fifo_rx_unit_array_reg_2_4_308
);
uart_unit_fifo_rx_unit_array_reg_2_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(3),
Q => uart_unit_fifo_rx_unit_array_reg_2_3_307
);
uart_unit_fifo_rx_unit_array_reg_2_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(2),
Q => uart_unit_fifo_rx_unit_array_reg_2_2_306
);
uart_unit_fifo_rx_unit_array_reg_2_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(1),
Q => uart_unit_fifo_rx_unit_array_reg_2_1_305
);
uart_unit_fifo_rx_unit_array_reg_2_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_rx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => uart_unit_uart_rx_unit_b_reg(0),
Q => uart_unit_fifo_rx_unit_array_reg_2_0_304
);
uart_unit_fifo_tx_unit_Mmux_r_data_3 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_0_369,
I2 => uart_unit_fifo_tx_unit_array_reg_3_0_378,
O => uart_unit_fifo_tx_unit_Mmux_r_data_3_334
);
uart_unit_fifo_tx_unit_Mmux_r_data_4 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_0_351,
I2 => uart_unit_fifo_tx_unit_array_reg_1_0_360,
O => uart_unit_fifo_tx_unit_Mmux_r_data_4_342
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_4_342,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_3_334,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(0)
);
uart_unit_fifo_tx_unit_Mmux_r_data_31 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_1_370,
I2 => uart_unit_fifo_tx_unit_array_reg_3_1_379,
O => uart_unit_fifo_tx_unit_Mmux_r_data_31_335
);
uart_unit_fifo_tx_unit_Mmux_r_data_41 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_1_352,
I2 => uart_unit_fifo_tx_unit_array_reg_1_1_361,
O => uart_unit_fifo_tx_unit_Mmux_r_data_41_343
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5_0 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_41_343,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_31_335,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(1)
);
uart_unit_fifo_tx_unit_Mmux_r_data_32 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_2_371,
I2 => uart_unit_fifo_tx_unit_array_reg_3_2_380,
O => uart_unit_fifo_tx_unit_Mmux_r_data_32_336
);
uart_unit_fifo_tx_unit_Mmux_r_data_42 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_2_353,
I2 => uart_unit_fifo_tx_unit_array_reg_1_2_362,
O => uart_unit_fifo_tx_unit_Mmux_r_data_42_344
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5_1 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_42_344,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_32_336,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(2)
);
uart_unit_fifo_tx_unit_Mmux_r_data_33 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_3_372,
I2 => uart_unit_fifo_tx_unit_array_reg_3_3_381,
O => uart_unit_fifo_tx_unit_Mmux_r_data_33_337
);
uart_unit_fifo_tx_unit_Mmux_r_data_43 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_3_354,
I2 => uart_unit_fifo_tx_unit_array_reg_1_3_363,
O => uart_unit_fifo_tx_unit_Mmux_r_data_43_345
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5_2 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_43_345,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_33_337,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(3)
);
uart_unit_fifo_tx_unit_Mmux_r_data_34 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_4_373,
I2 => uart_unit_fifo_tx_unit_array_reg_3_4_382,
O => uart_unit_fifo_tx_unit_Mmux_r_data_34_338
);
uart_unit_fifo_tx_unit_Mmux_r_data_44 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_4_355,
I2 => uart_unit_fifo_tx_unit_array_reg_1_4_364,
O => uart_unit_fifo_tx_unit_Mmux_r_data_44_346
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5_3 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_44_346,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_34_338,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(4)
);
uart_unit_fifo_tx_unit_Mmux_r_data_35 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_5_374,
I2 => uart_unit_fifo_tx_unit_array_reg_3_5_383,
O => uart_unit_fifo_tx_unit_Mmux_r_data_35_339
);
uart_unit_fifo_tx_unit_Mmux_r_data_45 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_5_356,
I2 => uart_unit_fifo_tx_unit_array_reg_1_5_365,
O => uart_unit_fifo_tx_unit_Mmux_r_data_45_347
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5_4 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_45_347,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_35_339,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(5)
);
uart_unit_fifo_tx_unit_Mmux_r_data_36 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_6_375,
I2 => uart_unit_fifo_tx_unit_array_reg_3_6_384,
O => uart_unit_fifo_tx_unit_Mmux_r_data_36_340
);
uart_unit_fifo_tx_unit_Mmux_r_data_46 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_6_357,
I2 => uart_unit_fifo_tx_unit_array_reg_1_6_366,
O => uart_unit_fifo_tx_unit_Mmux_r_data_46_348
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5_5 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_46_348,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_36_340,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(6)
);
uart_unit_fifo_tx_unit_Mmux_r_data_37 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_2_7_376,
I2 => uart_unit_fifo_tx_unit_array_reg_3_7_385,
O => uart_unit_fifo_tx_unit_Mmux_r_data_37_341
);
uart_unit_fifo_tx_unit_Mmux_r_data_47 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_array_reg_0_7_358,
I2 => uart_unit_fifo_tx_unit_array_reg_1_7_367,
O => uart_unit_fifo_tx_unit_Mmux_r_data_47_349
);
uart_unit_fifo_tx_unit_Mmux_r_data_2_f5_6 : MUXF5
port map (
I0 => uart_unit_fifo_tx_unit_Mmux_r_data_47_349,
I1 => uart_unit_fifo_tx_unit_Mmux_r_data_37_341,
S => uart_unit_fifo_tx_unit_r_ptr_reg(1),
O => uart_unit_tx_fifo_out(7)
);
uart_unit_fifo_tx_unit_r_ptr_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_tx_unit_r_ptr_reg_mux0000(1),
Q => uart_unit_fifo_tx_unit_r_ptr_reg(1)
);
uart_unit_fifo_tx_unit_r_ptr_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_tx_unit_r_ptr_reg_mux0000(0),
Q => uart_unit_fifo_tx_unit_r_ptr_reg(0)
);
uart_unit_fifo_tx_unit_w_ptr_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_tx_unit_w_ptr_reg_mux0000(1),
Q => uart_unit_fifo_tx_unit_w_ptr_reg(1)
);
uart_unit_fifo_tx_unit_w_ptr_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_tx_unit_w_ptr_reg_mux0000(0),
Q => uart_unit_fifo_tx_unit_w_ptr_reg(0)
);
uart_unit_fifo_tx_unit_full_reg : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_fifo_tx_unit_full_reg_mux0000,
Q => uart_unit_fifo_tx_unit_full_reg_389
);
uart_unit_fifo_tx_unit_empty_reg : FDP
port map (
C => clk_BUFGP_216,
D => uart_unit_fifo_tx_unit_empty_reg_mux0000,
PRE => reset_IBUF_234,
Q => uart_unit_fifo_tx_unit_empty_reg_387
);
uart_unit_fifo_tx_unit_array_reg_3_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(7),
Q => uart_unit_fifo_tx_unit_array_reg_3_7_385
);
uart_unit_fifo_tx_unit_array_reg_3_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(6),
Q => uart_unit_fifo_tx_unit_array_reg_3_6_384
);
uart_unit_fifo_tx_unit_array_reg_3_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(5),
Q => uart_unit_fifo_tx_unit_array_reg_3_5_383
);
uart_unit_fifo_tx_unit_array_reg_3_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(4),
Q => uart_unit_fifo_tx_unit_array_reg_3_4_382
);
uart_unit_fifo_tx_unit_array_reg_3_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(3),
Q => uart_unit_fifo_tx_unit_array_reg_3_3_381
);
uart_unit_fifo_tx_unit_array_reg_3_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(2),
Q => uart_unit_fifo_tx_unit_array_reg_3_2_380
);
uart_unit_fifo_tx_unit_array_reg_3_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(1),
Q => uart_unit_fifo_tx_unit_array_reg_3_1_379
);
uart_unit_fifo_tx_unit_array_reg_3_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_3_and0000,
CLR => reset_IBUF_234,
D => rec_data1(0),
Q => uart_unit_fifo_tx_unit_array_reg_3_0_378
);
uart_unit_fifo_tx_unit_array_reg_1_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(7),
Q => uart_unit_fifo_tx_unit_array_reg_1_7_367
);
uart_unit_fifo_tx_unit_array_reg_1_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(6),
Q => uart_unit_fifo_tx_unit_array_reg_1_6_366
);
uart_unit_fifo_tx_unit_array_reg_1_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(5),
Q => uart_unit_fifo_tx_unit_array_reg_1_5_365
);
uart_unit_fifo_tx_unit_array_reg_1_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(4),
Q => uart_unit_fifo_tx_unit_array_reg_1_4_364
);
uart_unit_fifo_tx_unit_array_reg_1_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(3),
Q => uart_unit_fifo_tx_unit_array_reg_1_3_363
);
uart_unit_fifo_tx_unit_array_reg_1_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(2),
Q => uart_unit_fifo_tx_unit_array_reg_1_2_362
);
uart_unit_fifo_tx_unit_array_reg_1_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(1),
Q => uart_unit_fifo_tx_unit_array_reg_1_1_361
);
uart_unit_fifo_tx_unit_array_reg_1_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_1_and0000,
CLR => reset_IBUF_234,
D => rec_data1(0),
Q => uart_unit_fifo_tx_unit_array_reg_1_0_360
);
uart_unit_fifo_tx_unit_array_reg_0_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(7),
Q => uart_unit_fifo_tx_unit_array_reg_0_7_358
);
uart_unit_fifo_tx_unit_array_reg_0_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(6),
Q => uart_unit_fifo_tx_unit_array_reg_0_6_357
);
uart_unit_fifo_tx_unit_array_reg_0_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(5),
Q => uart_unit_fifo_tx_unit_array_reg_0_5_356
);
uart_unit_fifo_tx_unit_array_reg_0_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(4),
Q => uart_unit_fifo_tx_unit_array_reg_0_4_355
);
uart_unit_fifo_tx_unit_array_reg_0_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(3),
Q => uart_unit_fifo_tx_unit_array_reg_0_3_354
);
uart_unit_fifo_tx_unit_array_reg_0_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(2),
Q => uart_unit_fifo_tx_unit_array_reg_0_2_353
);
uart_unit_fifo_tx_unit_array_reg_0_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(1),
Q => uart_unit_fifo_tx_unit_array_reg_0_1_352
);
uart_unit_fifo_tx_unit_array_reg_0_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_0_and0000,
CLR => reset_IBUF_234,
D => rec_data1(0),
Q => uart_unit_fifo_tx_unit_array_reg_0_0_351
);
uart_unit_fifo_tx_unit_array_reg_2_7 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(7),
Q => uart_unit_fifo_tx_unit_array_reg_2_7_376
);
uart_unit_fifo_tx_unit_array_reg_2_6 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(6),
Q => uart_unit_fifo_tx_unit_array_reg_2_6_375
);
uart_unit_fifo_tx_unit_array_reg_2_5 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(5),
Q => uart_unit_fifo_tx_unit_array_reg_2_5_374
);
uart_unit_fifo_tx_unit_array_reg_2_4 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(4),
Q => uart_unit_fifo_tx_unit_array_reg_2_4_373
);
uart_unit_fifo_tx_unit_array_reg_2_3 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(3),
Q => uart_unit_fifo_tx_unit_array_reg_2_3_372
);
uart_unit_fifo_tx_unit_array_reg_2_2 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(2),
Q => uart_unit_fifo_tx_unit_array_reg_2_2_371
);
uart_unit_fifo_tx_unit_array_reg_2_1 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(1),
Q => uart_unit_fifo_tx_unit_array_reg_2_1_370
);
uart_unit_fifo_tx_unit_array_reg_2_0 : FDCE
port map (
C => clk_BUFGP_216,
CE => uart_unit_fifo_tx_unit_array_reg_2_and0000,
CLR => reset_IBUF_234,
D => rec_data1(0),
Q => uart_unit_fifo_tx_unit_array_reg_2_0_369
);
uart_unit_uart_tx_unit_state_reg_FSM_FFd2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In,
Q => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506
);
uart_unit_uart_tx_unit_state_reg_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_In,
Q => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504
);
uart_unit_uart_tx_unit_s_reg_3 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_s_reg_mux0000(0),
Q => uart_unit_uart_tx_unit_s_reg(3)
);
uart_unit_uart_tx_unit_s_reg_2 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_s_reg_mux0000(1),
Q => uart_unit_uart_tx_unit_s_reg(2)
);
uart_unit_uart_tx_unit_s_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_s_reg_mux0000(2),
Q => uart_unit_uart_tx_unit_s_reg(1)
);
uart_unit_uart_tx_unit_s_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_s_reg_mux0000(3),
Q => uart_unit_uart_tx_unit_s_reg(0)
);
uart_unit_uart_tx_unit_b_reg_7 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(7),
Q => uart_unit_uart_tx_unit_b_reg(7)
);
uart_unit_uart_tx_unit_b_reg_6 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(6),
Q => uart_unit_uart_tx_unit_b_reg(6)
);
uart_unit_uart_tx_unit_b_reg_5 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(5),
Q => uart_unit_uart_tx_unit_b_reg(5)
);
uart_unit_uart_tx_unit_b_reg_4 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(4),
Q => uart_unit_uart_tx_unit_b_reg(4)
);
uart_unit_uart_tx_unit_b_reg_3 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(3),
Q => uart_unit_uart_tx_unit_b_reg(3)
);
uart_unit_uart_tx_unit_b_reg_2 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(2),
Q => uart_unit_uart_tx_unit_b_reg(2)
);
uart_unit_uart_tx_unit_b_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(1),
Q => uart_unit_uart_tx_unit_b_reg(1)
);
uart_unit_uart_tx_unit_b_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_b_reg_mux0000(0),
Q => uart_unit_uart_tx_unit_b_reg(0)
);
uart_unit_uart_tx_unit_n_reg_2 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_n_reg_mux0000(2),
Q => uart_unit_uart_tx_unit_n_reg(2)
);
uart_unit_uart_tx_unit_n_reg_1 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_n_reg_mux0000(1),
Q => uart_unit_uart_tx_unit_n_reg(1)
);
uart_unit_uart_tx_unit_n_reg_0 : FDC
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => uart_unit_uart_tx_unit_n_reg_mux0000(0),
Q => uart_unit_uart_tx_unit_n_reg(0)
);
uart_unit_uart_tx_unit_tx_reg : FDP
port map (
C => clk_BUFGP_216,
D => uart_unit_uart_tx_unit_tx_next,
PRE => reset_IBUF_234,
Q => uart_unit_uart_tx_unit_tx_reg_512
);
btn_db_unit_state_reg_cmp_eq0000_wg_cy_0_Q : MUXCY
port map (
CI => sseg_0_OBUF_245,
DI => an_0_OBUF_90,
S => btn_db_unit_state_reg_cmp_eq0000_wg_lut(0),
O => btn_db_unit_state_reg_cmp_eq0000_wg_cy(0)
);
btn_db_unit_state_reg_cmp_eq0000_wg_lut_1_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => btn_db_unit_q_next(12),
I1 => btn_db_unit_q_next(13),
I2 => btn_db_unit_q_next(14),
I3 => btn_db_unit_q_next(16),
O => btn_db_unit_state_reg_cmp_eq0000_wg_lut(1)
);
btn_db_unit_state_reg_cmp_eq0000_wg_cy_1_Q : MUXCY
port map (
CI => btn_db_unit_state_reg_cmp_eq0000_wg_cy(0),
DI => an_0_OBUF_90,
S => btn_db_unit_state_reg_cmp_eq0000_wg_lut(1),
O => btn_db_unit_state_reg_cmp_eq0000_wg_cy(1)
);
btn_db_unit_state_reg_cmp_eq0000_wg_lut_2_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => btn_db_unit_q_next(9),
I1 => btn_db_unit_q_next(10),
I2 => btn_db_unit_q_next(11),
I3 => btn_db_unit_q_next(17),
O => btn_db_unit_state_reg_cmp_eq0000_wg_lut(2)
);
btn_db_unit_state_reg_cmp_eq0000_wg_cy_2_Q : MUXCY
port map (
CI => btn_db_unit_state_reg_cmp_eq0000_wg_cy(1),
DI => an_0_OBUF_90,
S => btn_db_unit_state_reg_cmp_eq0000_wg_lut(2),
O => btn_db_unit_state_reg_cmp_eq0000_wg_cy(2)
);
btn_db_unit_state_reg_cmp_eq0000_wg_lut_3_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => btn_db_unit_q_next(6),
I1 => btn_db_unit_q_next(7),
I2 => btn_db_unit_q_next(8),
I3 => btn_db_unit_q_next(18),
O => btn_db_unit_state_reg_cmp_eq0000_wg_lut(3)
);
btn_db_unit_state_reg_cmp_eq0000_wg_cy_3_Q : MUXCY
port map (
CI => btn_db_unit_state_reg_cmp_eq0000_wg_cy(2),
DI => an_0_OBUF_90,
S => btn_db_unit_state_reg_cmp_eq0000_wg_lut(3),
O => btn_db_unit_state_reg_cmp_eq0000_wg_cy(3)
);
btn_db_unit_state_reg_cmp_eq0000_wg_lut_4_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => btn_db_unit_q_next(3),
I1 => btn_db_unit_q_next(4),
I2 => btn_db_unit_q_next(5),
I3 => btn_db_unit_q_next(19),
O => btn_db_unit_state_reg_cmp_eq0000_wg_lut(4)
);
btn_db_unit_state_reg_cmp_eq0000_wg_cy_4_Q : MUXCY
port map (
CI => btn_db_unit_state_reg_cmp_eq0000_wg_cy(3),
DI => an_0_OBUF_90,
S => btn_db_unit_state_reg_cmp_eq0000_wg_lut(4),
O => btn_db_unit_state_reg_cmp_eq0000_wg_cy(4)
);
btn_db_unit_state_reg_cmp_eq0000_wg_cy_5_Q : MUXCY
port map (
CI => btn_db_unit_state_reg_cmp_eq0000_wg_cy(4),
DI => an_0_OBUF_90,
S => btn_db_unit_state_reg_cmp_eq0000_wg_lut(5),
O => btn_db_unit_state_reg_cmp_eq0000
);
uart_unit_uart_tx_unit_tx_next1 : LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I1 => uart_unit_uart_tx_unit_b_reg(0),
I2 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
O => uart_unit_uart_tx_unit_tx_next
);
Madd_rec_data1_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Madd_rec_data1_lut(1),
I1 => Madd_rec_data1_cy(0),
O => rec_data1(1)
);
Madd_rec_data1_xor_2_11 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => Madd_rec_data1_lut(2),
I1 => Madd_rec_data1_lut(1),
I2 => Madd_rec_data1_cy(0),
O => rec_data1(2)
);
Madd_rec_data1_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => Madd_rec_data1_lut(1),
I1 => Madd_rec_data1_lut(3),
I2 => Madd_rec_data1_cy(0),
I3 => Madd_rec_data1_lut(2),
O => rec_data1(3)
);
uart_unit_uart_tx_unit_b_reg_mux0000_0_21 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_fifo_tx_unit_empty_reg_387,
O => uart_unit_uart_tx_unit_N6
);
uart_unit_baud_gen_unit_r_next_5_1 : LUT4
generic map(
INIT => X"1444"
)
port map (
I0 => uart_unit_tick,
I1 => uart_unit_baud_gen_unit_r_reg(5),
I2 => uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_3_Q,
I3 => uart_unit_baud_gen_unit_r_reg(4),
O => uart_unit_baud_gen_unit_r_next(5)
);
uart_unit_baud_gen_unit_r_next_2_1 : LUT4
generic map(
INIT => X"1444"
)
port map (
I0 => uart_unit_tick,
I1 => uart_unit_baud_gen_unit_r_reg(2),
I2 => uart_unit_baud_gen_unit_r_reg(0),
I3 => uart_unit_baud_gen_unit_r_reg(1),
O => uart_unit_baud_gen_unit_r_next(2)
);
uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_5_11 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_3_Q,
I1 => uart_unit_baud_gen_unit_r_reg(4),
I2 => uart_unit_baud_gen_unit_r_reg(5),
O => uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_5_Q
);
uart_unit_uart_rx_unit_s_reg_mux0000_3_211 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(2),
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I2 => uart_unit_uart_rx_unit_s_reg(3),
I3 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
O => uart_unit_uart_rx_unit_N21
);
uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_3_11 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_baud_gen_unit_r_reg(2),
I1 => uart_unit_baud_gen_unit_r_reg(3),
I2 => uart_unit_baud_gen_unit_r_reg(0),
I3 => uart_unit_baud_gen_unit_r_reg(1),
O => uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_3_Q
);
uart_unit_baud_gen_unit_r_next_7_1 : LUT4
generic map(
INIT => X"1444"
)
port map (
I0 => uart_unit_tick,
I1 => uart_unit_baud_gen_unit_r_reg(7),
I2 => uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_5_Q,
I3 => uart_unit_baud_gen_unit_r_reg(6),
O => uart_unit_baud_gen_unit_r_next(7)
);
uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In12 : LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I1 => uart_unit_uart_tx_unit_n_reg(2),
I2 => uart_unit_uart_tx_unit_n_reg(1),
I3 => uart_unit_uart_tx_unit_n_reg(0),
O => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In12_508
);
Madd_rec_data1_xor_4_12 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => Madd_rec_data1_lut(4),
I1 => N4,
O => rec_data1(4)
);
Madd_rec_data1_xor_5_11 : LUT3
generic map(
INIT => X"A6"
)
port map (
I0 => Madd_rec_data1_lut(5),
I1 => Madd_rec_data1_lut(4),
I2 => N4,
O => rec_data1(5)
);
uart_unit_uart_tx_unit_s_reg_mux0000_0_21 : LUT3
generic map(
INIT => X"72"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I1 => N151,
I2 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
O => uart_unit_uart_tx_unit_N3
);
uart_unit_uart_tx_unit_s_reg_mux0000_3_Q : LUT4
generic map(
INIT => X"FF8B"
)
port map (
I0 => N148,
I1 => uart_unit_uart_tx_unit_s_reg(0),
I2 => N10,
I3 => uart_unit_tx_done_tick,
O => uart_unit_uart_tx_unit_s_reg_mux0000(3)
);
uart_unit_uart_rx_unit_s_reg_mux0000_3_6 : LUT3
generic map(
INIT => X"32"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I1 => uart_unit_uart_rx_unit_s_reg(0),
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
O => uart_unit_uart_rx_unit_s_reg_mux0000_3_6_448
);
uart_unit_uart_rx_unit_s_reg_mux0000_3_14 : LUT4
generic map(
INIT => X"A888"
)
port map (
I0 => uart_unit_tick,
I1 => uart_unit_uart_rx_unit_s_reg_mux0000_3_6_448,
I2 => uart_unit_uart_rx_unit_s_reg(1),
I3 => uart_unit_uart_rx_unit_N21,
O => uart_unit_uart_rx_unit_s_reg_mux0000_3_14_447
);
uart_unit_uart_rx_unit_s_reg_mux0000_3_19 : LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg_mux0000_3_14_447,
I1 => uart_unit_uart_rx_unit_s_reg(0),
I2 => uart_unit_uart_rx_unit_N15,
O => uart_unit_uart_rx_unit_s_reg_mux0000(3)
);
uart_unit_uart_tx_unit_s_reg_mux0000_1_49 : LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => uart_unit_tx_done_tick,
I1 => uart_unit_uart_tx_unit_s_reg(2),
I2 => uart_unit_uart_tx_unit_N2,
I3 => uart_unit_uart_tx_unit_s_reg_mux0000_1_27_497,
O => uart_unit_uart_tx_unit_s_reg_mux0000(1)
);
uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In12 : LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I1 => uart_unit_uart_rx_unit_n_reg(2),
I2 => uart_unit_uart_rx_unit_n_reg(1),
I3 => uart_unit_uart_rx_unit_n_reg(0),
O => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In12_453
);
uart_unit_uart_rx_unit_n_reg_mux0000_0_21 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I2 => uart_unit_uart_rx_unit_state_reg_cmp_eq0001,
I3 => uart_unit_tick,
O => uart_unit_uart_rx_unit_b_reg_not0001
);
uart_unit_uart_rx_unit_s_reg_mux0000_0_11 : LUT4
generic map(
INIT => X"FC64"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(3),
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I3 => N155,
O => uart_unit_uart_rx_unit_N01
);
uart_unit_uart_rx_unit_s_reg_mux0000_1_SW0 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_tick,
I1 => uart_unit_uart_rx_unit_s_reg(1),
I2 => uart_unit_uart_rx_unit_s_reg(0),
I3 => uart_unit_uart_rx_unit_N01,
O => N20
);
uart_unit_uart_rx_unit_s_reg_mux0000_1_Q : LUT4
generic map(
INIT => X"FEF4"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(2),
I1 => N20,
I2 => uart_unit_rx_done_tick,
I3 => N21,
O => uart_unit_uart_rx_unit_s_reg_mux0000(1)
);
uart_unit_uart_rx_unit_s_reg_mux0000_2_16 : LUT3
generic map(
INIT => X"02"
)
port map (
I0 => rx_IBUF_236,
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
O => uart_unit_uart_rx_unit_s_reg_mux0000_2_16_442
);
uart_unit_uart_rx_unit_s_reg_mux0000_2_44 : LUT4
generic map(
INIT => X"FF32"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I1 => uart_unit_uart_rx_unit_s_reg(1),
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I3 => uart_unit_uart_rx_unit_N21,
O => uart_unit_uart_rx_unit_s_reg_mux0000_2_44_443
);
uart_unit_uart_rx_unit_s_reg_mux0000_2_58 : LUT4
generic map(
INIT => X"FFA8"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(1),
I1 => uart_unit_uart_rx_unit_s_reg_mux0000_2_8_445,
I2 => uart_unit_uart_rx_unit_s_reg_mux0000_2_16_442,
I3 => uart_unit_uart_rx_unit_s_reg_mux0000_2_51_444,
O => uart_unit_uart_rx_unit_s_reg_mux0000(2)
);
uart_unit_uart_tx_unit_s_reg_mux0000_0_34 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => uart_unit_uart_tx_unit_s_reg(1),
I1 => uart_unit_uart_tx_unit_s_reg(3),
I2 => uart_unit_uart_tx_unit_s_reg(0),
I3 => uart_unit_uart_tx_unit_s_reg(2),
O => uart_unit_uart_tx_unit_s_reg_mux0000_0_34_494
);
uart_unit_uart_tx_unit_s_reg_mux0000_0_50 : LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => uart_unit_tx_done_tick,
I1 => uart_unit_uart_tx_unit_s_reg(3),
I2 => uart_unit_uart_tx_unit_N2,
I3 => uart_unit_uart_tx_unit_s_reg_mux0000_0_37_495,
O => uart_unit_uart_tx_unit_s_reg_mux0000(0)
);
uart_unit_uart_tx_unit_s_reg_mux0000_2_8 : LUT4
generic map(
INIT => X"32FA"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I1 => uart_unit_uart_tx_unit_s_reg(0),
I2 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I3 => uart_unit_tick,
O => uart_unit_uart_tx_unit_s_reg_mux0000_2_8_502
);
uart_unit_uart_tx_unit_s_reg_mux0000_2_19 : LUT4
generic map(
INIT => X"E444"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I1 => uart_unit_fifo_tx_unit_empty_reg_387,
I2 => uart_unit_uart_tx_unit_s_reg(3),
I3 => uart_unit_uart_tx_unit_s_reg(2),
O => uart_unit_uart_tx_unit_s_reg_mux0000_2_19_499
);
uart_unit_uart_rx_unit_n_reg_mux0000_2_8 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I2 => uart_unit_uart_rx_unit_s_reg(3),
I3 => uart_unit_uart_rx_unit_N6,
O => uart_unit_uart_rx_unit_n_reg_mux0000_2_8_431
);
uart_unit_uart_rx_unit_s_reg_mux0000_0_71 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(1),
I1 => uart_unit_uart_rx_unit_s_reg(0),
I2 => uart_unit_uart_rx_unit_s_reg(2),
I3 => uart_unit_uart_rx_unit_s_reg(3),
O => uart_unit_uart_rx_unit_s_reg_mux0000_0_7
);
uart_unit_uart_rx_unit_s_reg_mux0000_0_31 : LUT4
generic map(
INIT => X"AA80"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(3),
I1 => uart_unit_uart_rx_unit_N6,
I2 => uart_unit_uart_rx_unit_N01,
I3 => N149,
O => uart_unit_uart_rx_unit_s_reg_mux0000_0_31_438
);
uart_unit_uart_rx_unit_s_reg_mux0000_0_32 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg_mux0000_0_31_438,
I1 => uart_unit_uart_rx_unit_s_reg_mux0000_0_21_437,
O => uart_unit_uart_rx_unit_s_reg_mux0000(0)
);
uart_unit_fifo_rx_unit_array_reg_3_and00001 : LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_full_reg_324,
I3 => uart_unit_rx_done_tick,
O => uart_unit_fifo_rx_unit_array_reg_3_and0000
);
uart_unit_fifo_rx_unit_array_reg_2_and00001 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_full_reg_324,
I3 => uart_unit_rx_done_tick,
O => uart_unit_fifo_rx_unit_array_reg_2_and0000
);
uart_unit_fifo_rx_unit_array_reg_1_and00001 : LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_full_reg_324,
I3 => uart_unit_rx_done_tick,
O => uart_unit_fifo_rx_unit_array_reg_1_and0000
);
uart_unit_fifo_rx_unit_array_reg_0_and00001 : LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_full_reg_324,
I3 => uart_unit_rx_done_tick,
O => uart_unit_fifo_rx_unit_array_reg_0_and0000
);
Madd_rec_data1_xor_4_111 : LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => Madd_rec_data1_lut(1),
I1 => Madd_rec_data1_cy(0),
I2 => Madd_rec_data1_lut(3),
I3 => Madd_rec_data1_lut(2),
O => N4
);
uart_unit_uart_tx_unit_b_reg_mux0000_7_1 : LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_uart_tx_unit_b_reg(7),
I1 => uart_unit_uart_tx_unit_N01,
I2 => uart_unit_tx_fifo_out(7),
I3 => uart_unit_uart_tx_unit_N6,
O => uart_unit_uart_tx_unit_b_reg_mux0000(7)
);
uart_unit_uart_tx_unit_b_reg_mux0000_0_11 : LUT4
generic map(
INIT => X"FE54"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I2 => uart_unit_fifo_tx_unit_empty_reg_387,
I3 => N159,
O => uart_unit_uart_tx_unit_N01
);
uart_unit_uart_tx_unit_b_reg_mux0000_6_Q : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_b_reg(7),
I3 => N23,
O => uart_unit_uart_tx_unit_b_reg_mux0000(6)
);
uart_unit_uart_tx_unit_b_reg_mux0000_5_Q : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_b_reg(6),
I3 => N25,
O => uart_unit_uart_tx_unit_b_reg_mux0000(5)
);
uart_unit_uart_tx_unit_b_reg_mux0000_4_Q : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_b_reg(5),
I3 => N27,
O => uart_unit_uart_tx_unit_b_reg_mux0000(4)
);
uart_unit_uart_tx_unit_b_reg_mux0000_3_Q : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_b_reg(4),
I3 => N29,
O => uart_unit_uart_tx_unit_b_reg_mux0000(3)
);
uart_unit_uart_tx_unit_b_reg_mux0000_2_Q : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_b_reg(3),
I3 => N31,
O => uart_unit_uart_tx_unit_b_reg_mux0000(2)
);
uart_unit_uart_tx_unit_b_reg_mux0000_1_Q : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_b_reg(2),
I3 => N33,
O => uart_unit_uart_tx_unit_b_reg_mux0000(1)
);
uart_unit_uart_tx_unit_b_reg_mux0000_0_Q : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_b_reg(1),
I3 => N35,
O => uart_unit_uart_tx_unit_b_reg_mux0000(0)
);
uart_unit_uart_rx_unit_n_reg_mux0000_0_SW0 : LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I1 => N158,
I2 => uart_unit_uart_rx_unit_n_reg(2),
I3 => uart_unit_uart_rx_unit_n_reg(1),
O => N37
);
uart_unit_uart_rx_unit_n_reg_mux0000_0_Q : LUT4
generic map(
INIT => X"FDA8"
)
port map (
I0 => uart_unit_uart_rx_unit_n_reg(0),
I1 => N150,
I2 => N37,
I3 => uart_unit_uart_rx_unit_b_reg_not0001,
O => uart_unit_uart_rx_unit_n_reg_mux0000(0)
);
uart_unit_uart_rx_unit_n_reg_mux0000_1_SW0 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => uart_unit_uart_rx_unit_n_reg(0),
I1 => uart_unit_uart_rx_unit_b_reg_not0001,
O => N39
);
uart_unit_uart_rx_unit_n_reg_mux0000_1_SW1 : LUT4
generic map(
INIT => X"AA2A"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I1 => uart_unit_uart_rx_unit_state_reg_cmp_eq0001,
I2 => uart_unit_uart_rx_unit_n_reg(0),
I3 => uart_unit_uart_rx_unit_n_reg(2),
O => N40
);
uart_unit_uart_rx_unit_n_reg_mux0000_1_Q : LUT4
generic map(
INIT => X"FDA8"
)
port map (
I0 => uart_unit_uart_rx_unit_n_reg(1),
I1 => uart_unit_uart_rx_unit_N16,
I2 => N40,
I3 => N39,
O => uart_unit_uart_rx_unit_n_reg_mux0000(1)
);
uart_unit_baud_gen_unit_r_next_cmp_eq000023 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => N153,
I1 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
O => uart_unit_tick
);
btn_db_unit_q_next_0_3 : LUT4
generic map(
INIT => X"FCFA"
)
port map (
I0 => btn_db_unit_q_reg(0),
I1 => btn_db_unit_q_next_share0000(0),
I2 => btn_db_unit_N11,
I3 => btn_db_unit_N01,
O => btn_db_unit_q_next(0)
);
btn_db_unit_q_next_0_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => btn_0_IBUF_92,
I1 => btn_db_unit_state_reg_FSM_FFd1_1_201,
O => btn_db_unit_N01
);
btn_db_unit_q_next_1_1 : LUT4
generic map(
INIT => X"FCFA"
)
port map (
I0 => btn_db_unit_q_reg(1),
I1 => btn_db_unit_q_next_share0000(1),
I2 => btn_db_unit_N11,
I3 => btn_db_unit_N01,
O => btn_db_unit_q_next(1)
);
btn_db_unit_state_reg_FSM_FFd1_In1 : LUT4
generic map(
INIT => X"E8CC"
)
port map (
I0 => btn_0_IBUF_92,
I1 => btn_db_unit_state_reg_FSM_FFd1_199,
I2 => btn_db_unit_state_reg_FSM_FFd2_202,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => btn_db_unit_state_reg_FSM_FFd1_In
);
btn_db_unit_q_next_3_1 : LUT4
generic map(
INIT => X"FCEE"
)
port map (
I0 => btn_db_unit_q_reg(3),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_q_next_share0000(3),
I3 => btn_db_unit_N01,
O => btn_db_unit_q_next(3)
);
btn_db_unit_q_next_2_1 : LUT4
generic map(
INIT => X"FCFA"
)
port map (
I0 => btn_db_unit_q_reg(2),
I1 => btn_db_unit_q_next_share0000(2),
I2 => btn_db_unit_N11,
I3 => btn_db_unit_N01,
O => btn_db_unit_q_next(2)
);
btn_db_unit_q_next_4_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(4),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(4),
O => btn_db_unit_q_next(4)
);
btn_db_unit_q_next_6_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(6),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(6),
O => btn_db_unit_q_next(6)
);
btn_db_unit_q_next_5_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(5),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(5),
O => btn_db_unit_q_next(5)
);
btn_db_unit_q_next_7_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(7),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(7),
O => btn_db_unit_q_next(7)
);
btn_db_unit_q_next_9_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(9),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(9),
O => btn_db_unit_q_next(9)
);
btn_db_unit_q_next_8_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(8),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(8),
O => btn_db_unit_q_next(8)
);
btn_db_unit_q_next_10_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(10),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(10),
O => btn_db_unit_q_next(10)
);
uart_unit_fifo_rx_unit_Mmux_r_ptr_reg_mux00006_SW0 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => uart_unit_fifo_rx_unit_empty_reg_322,
I1 => uart_unit_rx_done_tick,
O => N44
);
uart_unit_fifo_tx_unit_Mmux_full_reg_mux00003_SW0 : LUT2
generic map(
INIT => X"B"
)
port map (
I0 => uart_unit_fifo_tx_unit_empty_reg_387,
I1 => uart_unit_tx_done_tick,
O => N46
);
uart_unit_fifo_tx_unit_Mmux_full_reg_mux00003_SW1 : LUT4
generic map(
INIT => X"0024"
)
port map (
I0 => N146,
I1 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I3 => uart_unit_tx_done_tick,
O => N47
);
uart_unit_fifo_tx_unit_Mmux_empty_reg_mux00003_SW0 : LUT4
generic map(
INIT => X"1800"
)
port map (
I0 => uart_unit_fifo_tx_unit_N01,
I1 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I3 => N152,
O => N49
);
uart_unit_fifo_rx_unit_Mmux_full_reg_mux00003_SW0 : LUT4
generic map(
INIT => X"1800"
)
port map (
I0 => uart_unit_fifo_rx_unit_N01,
I1 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I3 => N156,
O => N52
);
uart_unit_fifo_rx_unit_Mmux_empty_reg_mux00003_SW0 : LUT2
generic map(
INIT => X"B"
)
port map (
I0 => uart_unit_fifo_rx_unit_full_reg_324,
I1 => uart_unit_rx_done_tick,
O => N55
);
uart_unit_fifo_rx_unit_Mmux_empty_reg_mux00003_SW1 : LUT4
generic map(
INIT => X"0024"
)
port map (
I0 => N147,
I1 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I3 => uart_unit_rx_done_tick,
O => N56
);
btn_db_unit_q_next_12_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(12),
I1 => N157,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(12),
O => btn_db_unit_q_next(12)
);
btn_db_unit_q_next_11_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(11),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(11),
O => btn_db_unit_q_next(11)
);
btn_db_unit_q_next_13_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(13),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(13),
O => btn_db_unit_q_next(13)
);
btn_db_unit_q_next_20_1 : LUT4
generic map(
INIT => X"FDF8"
)
port map (
I0 => btn_db_unit_N01,
I1 => btn_db_unit_q_next_share0000(20),
I2 => btn_db_unit_N11,
I3 => btn_db_unit_q_reg(20),
O => btn_db_unit_q_next(20)
);
btn_db_unit_q_next_19_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(19),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(19),
O => btn_db_unit_q_next(19)
);
btn_db_unit_q_next_18_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(18),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(18),
O => btn_db_unit_q_next(18)
);
btn_db_unit_q_next_17_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(17),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(17),
O => btn_db_unit_q_next(17)
);
btn_db_unit_q_next_16_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(16),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(16),
O => btn_db_unit_q_next(16)
);
btn_db_unit_q_next_14_1 : LUT4
generic map(
INIT => X"FECE"
)
port map (
I0 => btn_db_unit_q_reg(14),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(14),
O => btn_db_unit_q_next(14)
);
btn_db_unit_q_next_15_1 : LUT4
generic map(
INIT => X"FDF8"
)
port map (
I0 => btn_db_unit_N01,
I1 => btn_db_unit_q_next_share0000(15),
I2 => btn_db_unit_N11,
I3 => btn_db_unit_q_reg(15),
O => btn_db_unit_q_next(15)
);
reset_IBUF : IBUF
port map (
I => reset,
O => reset_IBUF_234
);
rx_IBUF : IBUF
port map (
I => rx,
O => rx_IBUF_236
);
btn_0_IBUF : IBUF
port map (
I => btn(0),
O => btn_0_IBUF_92
);
tx_OBUF : OBUF
port map (
I => uart_unit_uart_tx_unit_tx_reg_512,
O => tx
);
an_3_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => an(3)
);
an_2_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => an(2)
);
an_1_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => an(1)
);
an_0_OBUF : OBUF
port map (
I => an_0_OBUF_90,
O => an(0)
);
sseg_7_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => sseg(7)
);
sseg_6_OBUF : OBUF
port map (
I => sseg_6_OBUF_247,
O => sseg(6)
);
sseg_5_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => sseg(5)
);
sseg_4_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => sseg(4)
);
sseg_3_OBUF : OBUF
port map (
I => sseg_3_OBUF_246,
O => sseg(3)
);
sseg_2_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => sseg(2)
);
sseg_1_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => sseg(1)
);
sseg_0_OBUF : OBUF
port map (
I => sseg_0_OBUF_245,
O => sseg(0)
);
led_7_OBUF : OBUF
port map (
I => Madd_rec_data1_lut(7),
O => led(7)
);
led_6_OBUF : OBUF
port map (
I => Madd_rec_data1_lut(6),
O => led(6)
);
led_5_OBUF : OBUF
port map (
I => Madd_rec_data1_lut(5),
O => led(5)
);
led_4_OBUF : OBUF
port map (
I => Madd_rec_data1_lut(4),
O => led(4)
);
led_3_OBUF : OBUF
port map (
I => Madd_rec_data1_lut(3),
O => led(3)
);
led_2_OBUF : OBUF
port map (
I => Madd_rec_data1_lut(2),
O => led(2)
);
led_1_OBUF : OBUF
port map (
I => Madd_rec_data1_lut(1),
O => led(1)
);
led_0_OBUF : OBUF
port map (
I => Madd_rec_data1_cy(0),
O => led(0)
);
btn_db_unit_Msub_q_next_share0000_cy_0_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => btn_db_unit_q_reg(0),
O => btn_db_unit_Msub_q_next_share0000_cy_0_rt_94
);
btn_db_unit_state_reg_cmp_eq0000_wg_lut_0_Q : LUT4
generic map(
INIT => X"0131"
)
port map (
I0 => btn_db_unit_q_reg(15),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_N01,
I3 => btn_db_unit_q_next_share0000(15),
O => btn_db_unit_state_reg_cmp_eq0000_wg_lut(0)
);
btn_db_unit_state_reg_cmp_eq0000_wg_lut_5_Q : LUT4
generic map(
INIT => X"001D"
)
port map (
I0 => btn_db_unit_q_reg(20),
I1 => btn_db_unit_N01,
I2 => btn_db_unit_q_next_share0000(20),
I3 => N66,
O => btn_db_unit_state_reg_cmp_eq0000_wg_lut(5)
);
btn_db_unit_db_tick1_SW0 : LUT4
generic map(
INIT => X"F7FF"
)
port map (
I0 => uart_unit_fifo_tx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_tx_unit_full_reg_389,
I3 => btn_0_IBUF_92,
O => N68
);
uart_unit_fifo_tx_unit_array_reg_3_and00001 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => btn_db_unit_state_reg_FSM_FFd1_199,
I2 => N68,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_array_reg_3_and0000
);
btn_db_unit_db_tick1_SW1 : LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => uart_unit_fifo_tx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_tx_unit_full_reg_389,
I2 => btn_0_IBUF_92,
I3 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
O => N70
);
uart_unit_fifo_tx_unit_array_reg_2_and00001 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => btn_db_unit_state_reg_FSM_FFd1_199,
I2 => N70,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_array_reg_2_and0000
);
btn_db_unit_db_tick1_SW2 : LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
I1 => uart_unit_fifo_tx_unit_full_reg_389,
I2 => btn_0_IBUF_92,
I3 => uart_unit_fifo_tx_unit_w_ptr_reg(1),
O => N72
);
uart_unit_fifo_tx_unit_array_reg_1_and00001 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => btn_db_unit_state_reg_FSM_FFd1_199,
I2 => N72,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_array_reg_1_and0000
);
btn_db_unit_db_tick1_SW3 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
I1 => btn_0_IBUF_92,
I2 => uart_unit_fifo_tx_unit_full_reg_389,
I3 => uart_unit_fifo_tx_unit_w_ptr_reg(1),
O => N74
);
uart_unit_fifo_tx_unit_array_reg_0_and00001 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => btn_db_unit_state_reg_FSM_FFd1_199,
I2 => N74,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_array_reg_0_and0000
);
btn_db_unit_db_tick1_SW4 : LUT4
generic map(
INIT => X"0A02"
)
port map (
I0 => btn_0_IBUF_92,
I1 => uart_unit_fifo_tx_unit_full_reg_389,
I2 => btn_db_unit_state_reg_FSM_FFd1_199,
I3 => uart_unit_tx_done_tick,
O => N76
);
uart_unit_fifo_tx_unit_Mmux_w_ptr_reg_mux000021 : LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
I1 => btn_db_unit_state_reg_FSM_FFd2_202,
I2 => N76,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_w_ptr_reg_mux0000(0)
);
uart_unit_fifo_tx_unit_Mmux_r_ptr_reg_mux000031 : LUT4
generic map(
INIT => X"E4CC"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => N78,
I2 => N79,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_r_ptr_reg_mux0000(0)
);
btn_db_unit_db_tick1_SW7 : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I1 => uart_unit_fifo_rx_unit_full_reg_324,
I2 => uart_unit_rx_done_tick,
O => N81
);
uart_unit_fifo_rx_unit_Mmux_w_ptr_reg_mux000021 : LUT4
generic map(
INIT => X"E4CC"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => N81,
I2 => N82,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_rx_unit_w_ptr_reg_mux0000(0)
);
uart_unit_fifo_rx_unit_Mmux_r_ptr_reg_mux000031 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I2 => N84,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_rx_unit_r_ptr_reg_mux0000(0)
);
btn_db_unit_db_tick1_SW10 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => btn_0_IBUF_92,
I1 => btn_db_unit_state_reg_FSM_FFd2_202,
I2 => uart_unit_fifo_tx_unit_w_ptr_reg(0),
I3 => btn_db_unit_state_reg_FSM_FFd1_199,
O => N86
);
uart_unit_fifo_tx_unit_Mmux_w_ptr_reg_mux00004 : LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => uart_unit_fifo_tx_unit_w_ptr_reg(1),
I1 => N86,
I2 => N42,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_w_ptr_reg_mux0000(1)
);
btn_db_unit_db_tick1_SW11 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => btn_0_IBUF_92,
I1 => btn_db_unit_state_reg_FSM_FFd2_202,
I2 => uart_unit_fifo_rx_unit_r_ptr_reg(0),
I3 => btn_db_unit_state_reg_FSM_FFd1_199,
O => N88
);
uart_unit_fifo_rx_unit_Mmux_r_ptr_reg_mux00006 : LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(1),
I1 => N88,
I2 => N44,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_rx_unit_r_ptr_reg_mux0000(1)
);
uart_unit_fifo_tx_unit_Mmux_full_reg_mux00003 : LUT4
generic map(
INIT => X"EC4C"
)
port map (
I0 => btn_db_unit_state_reg_cmp_eq0000,
I1 => N90,
I2 => btn_db_unit_state_reg_FSM_FFd2_202,
I3 => N91,
O => uart_unit_fifo_tx_unit_full_reg_mux0000
);
uart_unit_fifo_tx_unit_Mmux_empty_reg_mux00003 : LUT4
generic map(
INIT => X"EC4C"
)
port map (
I0 => btn_db_unit_state_reg_cmp_eq0000,
I1 => N93,
I2 => btn_db_unit_state_reg_FSM_FFd2_202,
I3 => N94,
O => uart_unit_fifo_tx_unit_empty_reg_mux0000
);
uart_unit_fifo_rx_unit_Mmux_full_reg_mux00003 : LUT4
generic map(
INIT => X"EC4C"
)
port map (
I0 => btn_db_unit_state_reg_cmp_eq0000,
I1 => N96,
I2 => btn_db_unit_state_reg_FSM_FFd2_202,
I3 => N97,
O => uart_unit_fifo_rx_unit_full_reg_mux0000
);
uart_unit_fifo_rx_unit_Mmux_empty_reg_mux00003 : LUT4
generic map(
INIT => X"EC4C"
)
port map (
I0 => btn_db_unit_state_reg_cmp_eq0000,
I1 => N99,
I2 => btn_db_unit_state_reg_FSM_FFd2_202,
I3 => N100,
O => uart_unit_fifo_rx_unit_empty_reg_mux0000
);
uart_unit_fifo_tx_unit_Mmux_r_ptr_reg_mux00006 : LUT4
generic map(
INIT => X"E4CC"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => N102,
I2 => N103,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_tx_unit_r_ptr_reg_mux0000(1)
);
uart_unit_fifo_rx_unit_Mmux_w_ptr_reg_mux00004 : LUT4
generic map(
INIT => X"E4CC"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd2_202,
I1 => N105,
I2 => N106,
I3 => btn_db_unit_state_reg_cmp_eq0000,
O => uart_unit_fifo_rx_unit_w_ptr_reg_mux0000(1)
);
btn_db_unit_db_tick1_SW6_G : LUT4
generic map(
INIT => X"93C3"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd1_199,
I1 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I2 => uart_unit_fifo_tx_unit_empty_reg_387,
I3 => btn_0_IBUF_92,
O => N109
);
btn_db_unit_db_tick1_SW8_G : LUT4
generic map(
INIT => X"93C3"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd1_199,
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_full_reg_324,
I3 => btn_0_IBUF_92,
O => N111
);
btn_db_unit_db_tick1_SW21_F : LUT4
generic map(
INIT => X"93C3"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd1_199,
I1 => uart_unit_fifo_tx_unit_r_ptr_reg(1),
I2 => uart_unit_fifo_tx_unit_empty_reg_387,
I3 => btn_0_IBUF_92,
O => N120
);
btn_db_unit_db_tick1_SW23_F : LUT4
generic map(
INIT => X"93C3"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd1_199,
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
I2 => uart_unit_fifo_rx_unit_full_reg_324,
I3 => btn_0_IBUF_92,
O => N122
);
uart_unit_uart_rx_unit_n_reg_mux0000_2_26 : LUT4
generic map(
INIT => X"FF80"
)
port map (
I0 => uart_unit_uart_rx_unit_b_reg_not0001,
I1 => uart_unit_uart_rx_unit_n_reg(1),
I2 => uart_unit_uart_rx_unit_n_reg(0),
I3 => uart_unit_uart_rx_unit_n_reg_mux0000_2_18_430,
O => uart_unit_uart_rx_unit_n_reg_mux0000(2)
);
uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In45 : LUT3
generic map(
INIT => X"F1"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I1 => uart_unit_fifo_tx_unit_empty_reg_387,
I2 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In35_509,
O => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In
);
uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In45 : LUT3
generic map(
INIT => X"F1"
)
port map (
I0 => rx_IBUF_236,
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In35_454,
O => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In
);
Madd_rec_data1_xor_6_12 : LUT4
generic map(
INIT => X"CC6C"
)
port map (
I0 => Madd_rec_data1_lut(5),
I1 => Madd_rec_data1_lut(6),
I2 => Madd_rec_data1_lut(4),
I3 => N4,
O => rec_data1(6)
);
uart_unit_uart_tx_unit_state_reg_FSM_FFd1_In1 : LUT4
generic map(
INIT => X"EC4C"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_cmp_eq0000,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_tick,
I3 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
O => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_In
);
btn_db_unit_db_tick1_SW20 : LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(1),
I1 => uart_unit_fifo_tx_unit_empty_reg_387,
I2 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I3 => uart_unit_tx_done_tick,
O => N102
);
uart_unit_uart_tx_unit_s_reg_mux0000_3_SW0 : LUT4
generic map(
INIT => X"57FF"
)
port map (
I0 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I2 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I3 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
O => N10
);
uart_unit_baud_gen_unit_r_next_0_1 : LUT3
generic map(
INIT => X"13"
)
port map (
I0 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
I1 => uart_unit_baud_gen_unit_r_reg(0),
I2 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
O => uart_unit_baud_gen_unit_r_next(0)
);
uart_unit_baud_gen_unit_r_next_4_1 : LUT4
generic map(
INIT => X"143C"
)
port map (
I0 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I1 => uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_3_Q,
I2 => uart_unit_baud_gen_unit_r_reg(4),
I3 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
O => uart_unit_baud_gen_unit_r_next(4)
);
uart_unit_baud_gen_unit_r_next_1_1 : LUT4
generic map(
INIT => X"143C"
)
port map (
I0 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I1 => uart_unit_baud_gen_unit_r_reg(1),
I2 => uart_unit_baud_gen_unit_r_reg(0),
I3 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
O => uart_unit_baud_gen_unit_r_next(1)
);
uart_unit_uart_rx_unit_s_reg_mux0000_2_51 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I1 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
I2 => uart_unit_uart_rx_unit_s_reg(0),
I3 => uart_unit_uart_rx_unit_s_reg_mux0000_2_44_443,
O => uart_unit_uart_rx_unit_s_reg_mux0000_2_51_444
);
uart_unit_uart_rx_unit_n_reg_mux0000_2_18 : LUT4
generic map(
INIT => X"AA2A"
)
port map (
I0 => uart_unit_uart_rx_unit_n_reg(2),
I1 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I2 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
I3 => uart_unit_uart_rx_unit_n_reg_mux0000_2_8_431,
O => uart_unit_uart_rx_unit_n_reg_mux0000_2_18_430
);
uart_unit_uart_tx_unit_s_reg_mux0000_0_37 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_uart_tx_unit_s_reg_mux0000_0_34_494,
I1 => uart_unit_uart_tx_unit_N3,
I2 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I3 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
O => uart_unit_uart_tx_unit_s_reg_mux0000_0_37_495
);
uart_unit_uart_rx_unit_state_reg_FSM_FFd1_In : LUT4
generic map(
INIT => X"8AEA"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I2 => N128,
I3 => uart_unit_uart_rx_unit_s_reg(3),
O => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_In_450
);
uart_unit_baud_gen_unit_r_next_6_1 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => uart_unit_baud_gen_unit_r_reg(5),
I1 => uart_unit_baud_gen_unit_r_reg(6),
I2 => uart_unit_baud_gen_unit_r_reg(4),
I3 => uart_unit_baud_gen_unit_Madd_r_next_addsub0000_cy_3_Q,
O => uart_unit_baud_gen_unit_r_next(6)
);
uart_unit_uart_tx_unit_s_reg_mux0000_2_68_SW1 : LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I1 => N154,
I2 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I3 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
O => N130
);
uart_unit_baud_gen_unit_r_next_3_Q : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => uart_unit_baud_gen_unit_r_reg(0),
I1 => uart_unit_baud_gen_unit_r_reg(3),
I2 => uart_unit_baud_gen_unit_r_reg(1),
I3 => uart_unit_baud_gen_unit_r_reg(2),
O => uart_unit_baud_gen_unit_r_next(3)
);
btn_db_unit_db_tick1_SW61 : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I1 => N109,
I2 => uart_unit_tx_done_tick,
O => N79
);
btn_db_unit_db_tick1_SW81 : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I1 => N111,
I2 => uart_unit_rx_done_tick,
O => N82
);
btn_db_unit_db_tick1_SW231 : LUT4
generic map(
INIT => X"E2AA"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I2 => N122,
I3 => uart_unit_rx_done_tick,
O => N106
);
btn_db_unit_db_tick1_SW211 : LUT4
generic map(
INIT => X"E2AA"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(1),
I1 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I2 => N120,
I3 => uart_unit_tx_done_tick,
O => N103
);
btn_db_unit_state_reg_FSM_FFd1_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_216,
CLR => reset_IBUF_234,
D => btn_db_unit_state_reg_FSM_FFd1_In,
Q => btn_db_unit_state_reg_FSM_FFd1_1_201
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_216
);
btn_db_unit_Msub_q_next_share0000_lut_20_INV_0 : INV
port map (
I => btn_db_unit_q_reg(20),
O => btn_db_unit_Msub_q_next_share0000_lut(20)
);
btn_db_unit_Msub_q_next_share0000_lut_19_INV_0 : INV
port map (
I => btn_db_unit_q_reg(19),
O => btn_db_unit_Msub_q_next_share0000_lut(19)
);
btn_db_unit_Msub_q_next_share0000_lut_18_INV_0 : INV
port map (
I => btn_db_unit_q_reg(18),
O => btn_db_unit_Msub_q_next_share0000_lut(18)
);
btn_db_unit_Msub_q_next_share0000_lut_17_INV_0 : INV
port map (
I => btn_db_unit_q_reg(17),
O => btn_db_unit_Msub_q_next_share0000_lut(17)
);
btn_db_unit_Msub_q_next_share0000_lut_16_INV_0 : INV
port map (
I => btn_db_unit_q_reg(16),
O => btn_db_unit_Msub_q_next_share0000_lut(16)
);
btn_db_unit_Msub_q_next_share0000_lut_15_INV_0 : INV
port map (
I => btn_db_unit_q_reg(15),
O => btn_db_unit_Msub_q_next_share0000_lut(15)
);
btn_db_unit_Msub_q_next_share0000_lut_14_INV_0 : INV
port map (
I => btn_db_unit_q_reg(14),
O => btn_db_unit_Msub_q_next_share0000_lut(14)
);
btn_db_unit_Msub_q_next_share0000_lut_13_INV_0 : INV
port map (
I => btn_db_unit_q_reg(13),
O => btn_db_unit_Msub_q_next_share0000_lut(13)
);
btn_db_unit_Msub_q_next_share0000_lut_12_INV_0 : INV
port map (
I => btn_db_unit_q_reg(12),
O => btn_db_unit_Msub_q_next_share0000_lut(12)
);
btn_db_unit_Msub_q_next_share0000_lut_11_INV_0 : INV
port map (
I => btn_db_unit_q_reg(11),
O => btn_db_unit_Msub_q_next_share0000_lut(11)
);
btn_db_unit_Msub_q_next_share0000_lut_10_INV_0 : INV
port map (
I => btn_db_unit_q_reg(10),
O => btn_db_unit_Msub_q_next_share0000_lut(10)
);
btn_db_unit_Msub_q_next_share0000_lut_9_INV_0 : INV
port map (
I => btn_db_unit_q_reg(9),
O => btn_db_unit_Msub_q_next_share0000_lut(9)
);
btn_db_unit_Msub_q_next_share0000_lut_8_INV_0 : INV
port map (
I => btn_db_unit_q_reg(8),
O => btn_db_unit_Msub_q_next_share0000_lut(8)
);
btn_db_unit_Msub_q_next_share0000_lut_7_INV_0 : INV
port map (
I => btn_db_unit_q_reg(7),
O => btn_db_unit_Msub_q_next_share0000_lut(7)
);
btn_db_unit_Msub_q_next_share0000_lut_6_INV_0 : INV
port map (
I => btn_db_unit_q_reg(6),
O => btn_db_unit_Msub_q_next_share0000_lut(6)
);
btn_db_unit_Msub_q_next_share0000_lut_5_INV_0 : INV
port map (
I => btn_db_unit_q_reg(5),
O => btn_db_unit_Msub_q_next_share0000_lut(5)
);
btn_db_unit_Msub_q_next_share0000_lut_4_INV_0 : INV
port map (
I => btn_db_unit_q_reg(4),
O => btn_db_unit_Msub_q_next_share0000_lut(4)
);
btn_db_unit_Msub_q_next_share0000_lut_3_INV_0 : INV
port map (
I => btn_db_unit_q_reg(3),
O => btn_db_unit_Msub_q_next_share0000_lut(3)
);
btn_db_unit_Msub_q_next_share0000_lut_2_INV_0 : INV
port map (
I => btn_db_unit_q_reg(2),
O => btn_db_unit_Msub_q_next_share0000_lut(2)
);
btn_db_unit_Msub_q_next_share0000_lut_1_INV_0 : INV
port map (
I => btn_db_unit_q_reg(1),
O => btn_db_unit_Msub_q_next_share0000_lut(1)
);
sseg_not00031_INV_0 : INV
port map (
I => uart_unit_fifo_rx_unit_empty_reg_322,
O => sseg_3_OBUF_246
);
sseg_not00021_INV_0 : INV
port map (
I => uart_unit_fifo_tx_unit_full_reg_389,
O => sseg_6_OBUF_247
);
Madd_rec_data1_xor_0_11_INV_0 : INV
port map (
I => Madd_rec_data1_cy(0),
O => rec_data1(0)
);
btn_db_unit_db_tick1_SW15 : MUXF5
port map (
I0 => N136,
I1 => N137,
S => uart_unit_fifo_tx_unit_empty_reg_387,
O => N94
);
btn_db_unit_db_tick1_SW15_F : LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => N49,
I1 => btn_0_IBUF_92,
I2 => btn_db_unit_state_reg_FSM_FFd1_199,
O => N136
);
btn_db_unit_db_tick1_SW15_G : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => uart_unit_tx_done_tick,
I1 => btn_0_IBUF_92,
I2 => uart_unit_fifo_tx_unit_full_reg_389,
I3 => btn_db_unit_state_reg_FSM_FFd1_199,
O => N137
);
btn_db_unit_db_tick1_SW17 : MUXF5
port map (
I0 => N138,
I1 => N139,
S => uart_unit_fifo_rx_unit_full_reg_324,
O => N97
);
btn_db_unit_db_tick1_SW17_F : LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => N52,
I1 => btn_0_IBUF_92,
I2 => btn_db_unit_state_reg_FSM_FFd1_199,
O => N138
);
btn_db_unit_db_tick1_SW17_G : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => uart_unit_rx_done_tick,
I1 => btn_0_IBUF_92,
I2 => uart_unit_fifo_rx_unit_empty_reg_322,
I3 => btn_db_unit_state_reg_FSM_FFd1_199,
O => N139
);
btn_db_unit_db_tick1_SW19 : MUXF5
port map (
I0 => N140,
I1 => N141,
S => N55,
O => N100
);
btn_db_unit_db_tick1_SW19_F : LUT4
generic map(
INIT => X"0C08"
)
port map (
I0 => N56,
I1 => btn_0_IBUF_92,
I2 => btn_db_unit_state_reg_FSM_FFd1_199,
I3 => uart_unit_fifo_rx_unit_empty_reg_322,
O => N140
);
btn_db_unit_db_tick1_SW19_G : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd1_199,
I1 => btn_0_IBUF_92,
I2 => N56,
I3 => uart_unit_fifo_rx_unit_empty_reg_322,
O => N141
);
btn_db_unit_db_tick1_SW13 : MUXF5
port map (
I0 => N142,
I1 => N143,
S => N46,
O => N91
);
btn_db_unit_db_tick1_SW13_F : LUT4
generic map(
INIT => X"0C08"
)
port map (
I0 => N47,
I1 => btn_0_IBUF_92,
I2 => btn_db_unit_state_reg_FSM_FFd1_199,
I3 => uart_unit_fifo_tx_unit_full_reg_389,
O => N142
);
btn_db_unit_db_tick1_SW13_G : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => btn_db_unit_state_reg_FSM_FFd1_199,
I1 => btn_0_IBUF_92,
I2 => N47,
I3 => uart_unit_fifo_tx_unit_full_reg_389,
O => N143
);
btn_db_unit_q_next_20_1_SW0 : MUXF5
port map (
I0 => N144,
I1 => N145,
S => btn_db_unit_N01,
O => N66
);
btn_db_unit_q_next_20_1_SW0_F : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => btn_db_unit_N11,
I1 => btn_db_unit_q_reg(2),
I2 => btn_db_unit_q_reg(1),
I3 => btn_db_unit_q_reg(0),
O => N144
);
btn_db_unit_q_next_20_1_SW0_G : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => btn_db_unit_q_next_share0000(2),
I1 => btn_db_unit_N11,
I2 => btn_db_unit_q_next_share0000(1),
I3 => btn_db_unit_q_next_share0000(0),
O => N145
);
uart_unit_uart_tx_unit_n_reg_mux0000_2_1 : LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_n_reg(1),
I2 => uart_unit_uart_tx_unit_n_reg(0),
I3 => uart_unit_uart_tx_unit_n_reg(2),
O => uart_unit_uart_tx_unit_n_reg_mux0000_2_1_487
);
uart_unit_uart_tx_unit_n_reg_mux0000_2_2 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_n_reg(2),
O => uart_unit_uart_tx_unit_n_reg_mux0000_2_2_488
);
uart_unit_uart_tx_unit_n_reg_mux0000_2_f5 : MUXF5
port map (
I0 => uart_unit_uart_tx_unit_n_reg_mux0000_2_2_488,
I1 => uart_unit_uart_tx_unit_n_reg_mux0000_2_1_487,
S => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
O => uart_unit_uart_tx_unit_n_reg_mux0000(2)
);
uart_unit_uart_tx_unit_n_reg_mux0000_0_1 : LUT4
generic map(
INIT => X"EA55"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_n_reg(1),
I2 => uart_unit_uart_tx_unit_n_reg(2),
I3 => uart_unit_uart_tx_unit_n_reg(0),
O => uart_unit_uart_tx_unit_n_reg_mux0000_0_1_481
);
uart_unit_uart_tx_unit_n_reg_mux0000_0_2 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_n_reg(0),
O => uart_unit_uart_tx_unit_n_reg_mux0000_0_2_482
);
uart_unit_uart_tx_unit_n_reg_mux0000_0_f5 : MUXF5
port map (
I0 => uart_unit_uart_tx_unit_n_reg_mux0000_0_2_482,
I1 => uart_unit_uart_tx_unit_n_reg_mux0000_0_1_481,
S => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
O => uart_unit_uart_tx_unit_n_reg_mux0000(0)
);
uart_unit_uart_tx_unit_n_reg_mux0000_1_1 : LUT4
generic map(
INIT => X"F4B4"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_n_reg(0),
I2 => uart_unit_uart_tx_unit_n_reg(1),
I3 => uart_unit_uart_tx_unit_n_reg(2),
O => uart_unit_uart_tx_unit_n_reg_mux0000_1_1_484
);
uart_unit_uart_tx_unit_n_reg_mux0000_1_2 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => uart_unit_uart_tx_unit_N7,
I1 => uart_unit_uart_tx_unit_n_reg(1),
O => uart_unit_uart_tx_unit_n_reg_mux0000_1_2_485
);
uart_unit_uart_tx_unit_n_reg_mux0000_1_f5 : MUXF5
port map (
I0 => uart_unit_uart_tx_unit_n_reg_mux0000_1_2_485,
I1 => uart_unit_uart_tx_unit_n_reg_mux0000_1_1_484,
S => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
O => uart_unit_uart_tx_unit_n_reg_mux0000(1)
);
Madd_rec_data1_xor_7_111 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => Madd_rec_data1_lut(6),
I1 => Madd_rec_data1_lut(7),
I2 => Madd_rec_data1_lut(5),
I3 => Madd_rec_data1_lut(4),
O => Madd_rec_data1_xor_7_11
);
Madd_rec_data1_xor_7_11_f5 : MUXF5
port map (
I0 => Madd_rec_data1_xor_7_11,
I1 => Madd_rec_data1_lut(7),
S => N4,
O => rec_data1(7)
);
uart_unit_uart_tx_unit_s_reg_mux0000_2_681 : LUT3
generic map(
INIT => X"F2"
)
port map (
I0 => uart_unit_uart_tx_unit_s_reg_mux0000_2_19_499,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I2 => uart_unit_uart_tx_unit_s_reg_mux0000_2_8_502,
O => uart_unit_uart_tx_unit_s_reg_mux0000_2_68
);
uart_unit_uart_tx_unit_s_reg_mux0000_2_682 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => uart_unit_uart_tx_unit_s_reg(0),
I1 => N130,
O => uart_unit_uart_tx_unit_s_reg_mux0000_2_681_501
);
uart_unit_uart_tx_unit_s_reg_mux0000_2_68_f5 : MUXF5
port map (
I0 => uart_unit_uart_tx_unit_s_reg_mux0000_2_681_501,
I1 => uart_unit_uart_tx_unit_s_reg_mux0000_2_68,
S => uart_unit_uart_tx_unit_s_reg(1),
O => uart_unit_uart_tx_unit_s_reg_mux0000(2)
);
uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In35 : LUT4_L
generic map(
INIT => X"AA2A"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I1 => uart_unit_uart_tx_unit_state_reg_cmp_eq0000,
I2 => uart_unit_tick,
I3 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In12_508,
LO => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_In35_509
);
uart_unit_fifo_tx_unit_Mmux_empty_reg_mux0000311 : LUT2_D
generic map(
INIT => X"9"
)
port map (
I0 => uart_unit_fifo_tx_unit_r_ptr_reg(1),
I1 => uart_unit_fifo_tx_unit_w_ptr_reg(1),
LO => N146,
O => uart_unit_fifo_tx_unit_N01
);
uart_unit_fifo_rx_unit_Mmux_empty_reg_mux0000311 : LUT2_D
generic map(
INIT => X"9"
)
port map (
I0 => uart_unit_fifo_rx_unit_r_ptr_reg(1),
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
LO => N147,
O => uart_unit_fifo_rx_unit_N01
);
uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In35 : LUT4_L
generic map(
INIT => X"AA2A"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I1 => uart_unit_tick,
I2 => uart_unit_uart_rx_unit_state_reg_cmp_eq0001,
I3 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In12_453,
LO => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_In35_454
);
uart_unit_uart_tx_unit_s_reg_mux0000_0_11 : LUT4_D
generic map(
INIT => X"3732"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I1 => uart_unit_tick,
I2 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I3 => uart_unit_fifo_tx_unit_empty_reg_387,
LO => N148,
O => uart_unit_uart_tx_unit_N2
);
uart_unit_uart_rx_unit_s_reg_mux0000_3_15 : LUT4_D
generic map(
INIT => X"02FE"
)
port map (
I0 => rx_IBUF_236,
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I3 => uart_unit_tick,
LO => N149,
O => uart_unit_uart_rx_unit_N15
);
uart_unit_uart_rx_unit_n_reg_mux0000_0_11 : LUT4_D
generic map(
INIT => X"57FF"
)
port map (
I0 => uart_unit_tick,
I1 => uart_unit_uart_rx_unit_s_reg_mux0000_0_7,
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I3 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
LO => N150,
O => uart_unit_uart_rx_unit_N16
);
uart_unit_uart_rx_unit_s_reg_mux0000_1_SW1 : LUT4_L
generic map(
INIT => X"FF4C"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(1),
I1 => uart_unit_uart_rx_unit_N01,
I2 => uart_unit_uart_rx_unit_s_reg(0),
I3 => uart_unit_uart_rx_unit_N15,
LO => N21
);
uart_unit_uart_rx_unit_s_reg_mux0000_2_8 : LUT4_L
generic map(
INIT => X"32FA"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I1 => uart_unit_uart_rx_unit_s_reg(0),
I2 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I3 => uart_unit_tick,
LO => uart_unit_uart_rx_unit_s_reg_mux0000_2_8_445
);
uart_unit_uart_rx_unit_s_reg_mux0000_0_21 : LUT4_L
generic map(
INIT => X"FF80"
)
port map (
I0 => uart_unit_uart_rx_unit_N01,
I1 => uart_unit_tick,
I2 => uart_unit_uart_rx_unit_s_reg_mux0000_0_7,
I3 => uart_unit_rx_done_tick,
LO => uart_unit_uart_rx_unit_s_reg_mux0000_0_21_437
);
uart_unit_uart_tx_unit_state_reg_cmp_eq00001 : LUT4_D
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_uart_tx_unit_s_reg(1),
I1 => uart_unit_uart_tx_unit_s_reg(0),
I2 => uart_unit_uart_tx_unit_s_reg(3),
I3 => uart_unit_uart_tx_unit_s_reg(2),
LO => N151,
O => uart_unit_uart_tx_unit_state_reg_cmp_eq0000
);
uart_unit_uart_tx_unit_b_reg_mux0000_6_SW0 : LUT4_L
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_tx_fifo_out(6),
I1 => uart_unit_uart_tx_unit_N6,
I2 => uart_unit_uart_tx_unit_b_reg(6),
I3 => uart_unit_uart_tx_unit_N01,
LO => N23
);
uart_unit_uart_tx_unit_b_reg_mux0000_5_SW0 : LUT4_L
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_tx_fifo_out(5),
I1 => uart_unit_uart_tx_unit_N6,
I2 => uart_unit_uart_tx_unit_b_reg(5),
I3 => uart_unit_uart_tx_unit_N01,
LO => N25
);
uart_unit_uart_tx_unit_b_reg_mux0000_4_SW0 : LUT4_L
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_tx_fifo_out(4),
I1 => uart_unit_uart_tx_unit_N6,
I2 => uart_unit_uart_tx_unit_b_reg(4),
I3 => uart_unit_uart_tx_unit_N01,
LO => N27
);
uart_unit_uart_tx_unit_b_reg_mux0000_3_SW0 : LUT4_L
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_tx_fifo_out(3),
I1 => uart_unit_uart_tx_unit_N6,
I2 => uart_unit_uart_tx_unit_b_reg(3),
I3 => uart_unit_uart_tx_unit_N01,
LO => N29
);
uart_unit_uart_tx_unit_b_reg_mux0000_2_SW0 : LUT4_L
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_tx_fifo_out(2),
I1 => uart_unit_uart_tx_unit_N6,
I2 => uart_unit_uart_tx_unit_b_reg(2),
I3 => uart_unit_uart_tx_unit_N01,
LO => N31
);
uart_unit_uart_tx_unit_b_reg_mux0000_1_SW0 : LUT4_L
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_tx_fifo_out(1),
I1 => uart_unit_uart_tx_unit_N6,
I2 => uart_unit_uart_tx_unit_b_reg(1),
I3 => uart_unit_uart_tx_unit_N01,
LO => N33
);
uart_unit_uart_tx_unit_b_reg_mux0000_0_SW0 : LUT4_L
generic map(
INIT => X"F888"
)
port map (
I0 => uart_unit_tx_fifo_out(0),
I1 => uart_unit_uart_tx_unit_N6,
I2 => uart_unit_uart_tx_unit_b_reg(0),
I3 => uart_unit_uart_tx_unit_N01,
LO => N35
);
uart_unit_uart_tx_unit_tx_done_tick1 : LUT4_D
generic map(
INIT => X"4000"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I1 => uart_unit_uart_tx_unit_state_reg_FSM_FFd1_504,
I2 => uart_unit_uart_tx_unit_state_reg_cmp_eq0000,
I3 => uart_unit_tick,
LO => N152,
O => uart_unit_tx_done_tick
);
uart_unit_baud_gen_unit_r_next_cmp_eq000010 : LUT4_D
generic map(
INIT => X"0020"
)
port map (
I0 => uart_unit_baud_gen_unit_r_reg(7),
I1 => uart_unit_baud_gen_unit_r_reg(6),
I2 => uart_unit_baud_gen_unit_r_reg(5),
I3 => uart_unit_baud_gen_unit_r_reg(4),
LO => N153,
O => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259
);
uart_unit_baud_gen_unit_r_next_cmp_eq000022 : LUT4_D
generic map(
INIT => X"0010"
)
port map (
I0 => uart_unit_baud_gen_unit_r_reg(3),
I1 => uart_unit_baud_gen_unit_r_reg(2),
I2 => uart_unit_baud_gen_unit_r_reg(1),
I3 => uart_unit_baud_gen_unit_r_reg(0),
LO => N154,
O => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260
);
uart_unit_uart_rx_unit_s_reg_mux0000_0_41 : LUT3_D
generic map(
INIT => X"7F"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(0),
I1 => uart_unit_uart_rx_unit_s_reg(1),
I2 => uart_unit_uart_rx_unit_s_reg(2),
LO => N155,
O => uart_unit_uart_rx_unit_N6
);
uart_unit_uart_rx_unit_s_reg_mux0000_0_72 : LUT4_D
generic map(
INIT => X"4000"
)
port map (
I0 => uart_unit_uart_rx_unit_state_reg_FSM_FFd2_451,
I1 => uart_unit_uart_rx_unit_state_reg_FSM_FFd1_449,
I2 => uart_unit_uart_rx_unit_state_reg_cmp_eq0001,
I3 => uart_unit_tick,
LO => N156,
O => uart_unit_rx_done_tick
);
btn_db_unit_q_next_0_21 : LUT3_D
generic map(
INIT => X"42"
)
port map (
I0 => btn_0_IBUF_92,
I1 => btn_db_unit_state_reg_FSM_FFd2_202,
I2 => btn_db_unit_state_reg_FSM_FFd1_1_201,
LO => N157,
O => btn_db_unit_N11
);
uart_unit_fifo_tx_unit_Mmux_w_ptr_reg_mux00004_SW0 : LUT2_L
generic map(
INIT => X"D"
)
port map (
I0 => uart_unit_fifo_tx_unit_full_reg_389,
I1 => uart_unit_tx_done_tick,
LO => N42
);
btn_db_unit_db_tick1_SW5 : LUT3_L
generic map(
INIT => X"9C"
)
port map (
I0 => uart_unit_fifo_tx_unit_empty_reg_387,
I1 => uart_unit_fifo_tx_unit_r_ptr_reg(0),
I2 => uart_unit_tx_done_tick,
LO => N78
);
btn_db_unit_db_tick1_SW9 : LUT4_L
generic map(
INIT => X"0A02"
)
port map (
I0 => btn_0_IBUF_92,
I1 => uart_unit_fifo_rx_unit_empty_reg_322,
I2 => btn_db_unit_state_reg_FSM_FFd1_199,
I3 => uart_unit_rx_done_tick,
LO => N84
);
btn_db_unit_db_tick1_SW14 : LUT2_L
generic map(
INIT => X"E"
)
port map (
I0 => uart_unit_fifo_tx_unit_empty_reg_387,
I1 => N49,
LO => N93
);
btn_db_unit_db_tick1_SW16 : LUT2_L
generic map(
INIT => X"E"
)
port map (
I0 => uart_unit_fifo_rx_unit_full_reg_324,
I1 => N52,
LO => N96
);
uart_unit_uart_rx_unit_state_reg_cmp_eq00011 : LUT4_D
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_uart_rx_unit_s_reg(2),
I1 => uart_unit_uart_rx_unit_s_reg(3),
I2 => uart_unit_uart_rx_unit_s_reg(1),
I3 => uart_unit_uart_rx_unit_s_reg(0),
LO => N158,
O => uart_unit_uart_rx_unit_state_reg_cmp_eq0001
);
btn_db_unit_db_tick1_SW12 : LUT3_L
generic map(
INIT => X"8A"
)
port map (
I0 => uart_unit_fifo_tx_unit_full_reg_389,
I1 => uart_unit_fifo_tx_unit_empty_reg_387,
I2 => uart_unit_tx_done_tick,
LO => N90
);
btn_db_unit_db_tick1_SW18 : LUT3_L
generic map(
INIT => X"8A"
)
port map (
I0 => uart_unit_fifo_rx_unit_empty_reg_322,
I1 => uart_unit_fifo_rx_unit_full_reg_324,
I2 => uart_unit_rx_done_tick,
LO => N99
);
btn_db_unit_db_tick1_SW22 : LUT4_L
generic map(
INIT => X"A6AA"
)
port map (
I0 => uart_unit_fifo_rx_unit_w_ptr_reg(1),
I1 => uart_unit_fifo_rx_unit_w_ptr_reg(0),
I2 => uart_unit_fifo_rx_unit_full_reg_324,
I3 => uart_unit_rx_done_tick,
LO => N105
);
uart_unit_uart_rx_unit_state_reg_FSM_FFd1_In_SW1 : LUT4_L
generic map(
INIT => X"8000"
)
port map (
I0 => uart_unit_tick,
I1 => uart_unit_uart_rx_unit_s_reg(0),
I2 => uart_unit_uart_rx_unit_s_reg(1),
I3 => uart_unit_uart_rx_unit_s_reg(2),
LO => N128
);
uart_unit_uart_tx_unit_b_reg_mux0000_0_111 : LUT4_D
generic map(
INIT => X"7FFF"
)
port map (
I0 => uart_unit_uart_tx_unit_state_reg_FSM_FFd2_506,
I1 => uart_unit_uart_tx_unit_state_reg_cmp_eq0000,
I2 => uart_unit_baud_gen_unit_r_next_cmp_eq000010_259,
I3 => uart_unit_baud_gen_unit_r_next_cmp_eq000022_260,
LO => N159,
O => uart_unit_uart_tx_unit_N7
);
uart_unit_uart_tx_unit_s_reg_mux0000_1_27 : LUT4_L
generic map(
INIT => X"2888"
)
port map (
I0 => N130,
I1 => uart_unit_uart_tx_unit_s_reg(2),
I2 => uart_unit_uart_tx_unit_s_reg(0),
I3 => uart_unit_uart_tx_unit_s_reg(1),
LO => uart_unit_uart_tx_unit_s_reg_mux0000_1_27_497
);
end Structure;