Hochschule Kempten      
Fakultšt Elektrotechnik      
Microelectronics       Fachgebiet Elektronik, Prof. Vollrath      

Conversion Tool Xilinx ISE VHDL to Electric VHDL for Synthesis

Since Electric:
  • does not support STD_LOGIC, STD_LOGIC_VECTOR
  • does not have 4 input lookup tables as layout
this conversion tool is applied.
Xilinx Webpack output should be for Spartan 6 devices and primitives.
ToDo: Vivado primitives for Spartan 7. Setting of signals to '0' or '1'.

Please check that all used functions are listed in the componnent section.
Please remove the last semicolon at the end of the entity ports.
Please copy the components between architecture and signals.
This web page contains a UART example embedded in the webpage.

Summary Functions


Processed output

Data to process