Hochschule Kempten      
Fakultät Elektrotechnik      
Microelectronics       Fachgebiet Elektronik, Prof. Vollrath      

Conversion Tool Xilinx Vivado VHDL to Electric VHDL for Synthesis

Since Electric:
  • does not support STD_LOGIC, STD_LOGIC_VECTOR
  • does not have 4 input lookup tables as layout
this conversion tool is applied.
Xilinx Vivado output should be for BASYS3 (artix7) devices and primitives.

This web page contains a example embedded in the webpage.




Summary Functions

Entities


Processed output


Preprocessed output


Data to process