Conversion Tool Xilinx Vivado VHDL to Electric VHDL for Synthesis
Since Electric:
- does not support STD_LOGIC, STD_LOGIC_VECTOR
- does not have 4 input lookup tables as layout
this conversion tool is applied.
Xilinx Vivado output should be for BASYS3 (artix7) devices and primitives.
This web page contains a example embedded in the webpage.
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Summary Functions
Entities
Processed output
Preprocessed output
Data to process
entity serInvSer is
port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
te : in STD_LOGIC;
tdi : in STD_LOGIC;
tdo : out STD_LOGIC;
a : in STD_LOGIC_VECTOR ( 3 downto 0 );
y : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of serInvSer : entity is true;
end serInvSer;
architecture STRUCTURE of serInvSer is
signal a_IBUF : STD_LOGIC_VECTOR ( 0 to 0 );
signal busy_i_1_n_0 : STD_LOGIC;
signal busy_reg_n_0 : STD_LOGIC;
signal ce_IBUF : STD_LOGIC;
signal clk_IBUF : STD_LOGIC;
signal clk_IBUF_BUFG : STD_LOGIC;
signal \dd[0]_i_1_n_0\ : STD_LOGIC;
signal \dd[1]_i_1_n_0\ : STD_LOGIC;
signal \dd[2]_i_1_n_0\ : STD_LOGIC;
signal \dd_reg_n_0_[0]\ : STD_LOGIC;
signal \dd_reg_n_0_[1]\ : STD_LOGIC;
signal \dd_reg_n_0_[2]\ : STD_LOGIC;
signal ddx : STD_LOGIC;
signal \ddx[0]_i_1_n_0\ : STD_LOGIC;
signal \ddx[1]_i_1_n_0\ : STD_LOGIC;
signal \ddx[2]_i_1_n_0\ : STD_LOGIC;
signal \ddx[3]_i_2_n_0\ : STD_LOGIC;
signal \ddx_reg_n_0_[0]\ : STD_LOGIC;
signal \ddx_reg_n_0_[1]\ : STD_LOGIC;
signal \ddx_reg_n_0_[2]\ : STD_LOGIC;
signal \ddx_reg_n_0_[3]\ : STD_LOGIC;
signal pos : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \pos[0]_i_1_n_0\ : STD_LOGIC;
signal \pos[1]_i_1_n_0\ : STD_LOGIC;
signal \pos[2]_i_1_n_0\ : STD_LOGIC;
signal \pos[3]_i_1_n_0\ : STD_LOGIC;
signal rst_IBUF : STD_LOGIC;
signal tdo_OBUF : STD_LOGIC;
signal y_OBUF : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \yi[0]_i_1_n_0\ : STD_LOGIC;
signal \yi[2]_i_1_n_0\ : STD_LOGIC;
signal \yi[3]_i_1_n_0\ : STD_LOGIC;
signal \yi[3]_i_2_n_0\ : STD_LOGIC;
signal \yi[3]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dd[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \dd[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ddx[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \ddx[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ddx[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \ddx[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \pos[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \pos[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \yi[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \yi[3]_i_3\ : label is "soft_lutpair4";
begin
\a_IBUF[0]_inst\: unisim.vcomponents.IBUF
port map (
I => a(0),
O => a_IBUF(0)
);
busy_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0035F0F0"
)
port map (
I0 => a_IBUF(0),
I1 => pos(3),
I2 => busy_reg_n_0,
I3 => rst_IBUF,
I4 => ce_IBUF,
O => busy_i_1_n_0
);
busy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => '1',
D => busy_i_1_n_0,
Q => busy_reg_n_0,
R => '0'
);
ce_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => ce,
O => ce_IBUF
);
clk_IBUF_BUFG_inst: unisim.vcomponents.BUFG
port map (
I => clk_IBUF,
O => clk_IBUF_BUFG
);
clk_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => clk,
O => clk_IBUF
);
\dd[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4450"
)
port map (
I0 => rst_IBUF,
I1 => a_IBUF(0),
I2 => \dd_reg_n_0_[0]\,
I3 => busy_reg_n_0,
O => \dd[0]_i_1_n_0\
);
\dd[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4450"
)
port map (
I0 => rst_IBUF,
I1 => \dd_reg_n_0_[0]\,
I2 => \dd_reg_n_0_[1]\,
I3 => busy_reg_n_0,
O => \dd[1]_i_1_n_0\
);
\dd[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4450"
)
port map (
I0 => rst_IBUF,
I1 => \dd_reg_n_0_[1]\,
I2 => \dd_reg_n_0_[2]\,
I3 => busy_reg_n_0,
O => \dd[2]_i_1_n_0\
);
\dd_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ce_IBUF,
D => \dd[0]_i_1_n_0\,
Q => \dd_reg_n_0_[0]\,
R => '0'
);
\dd_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ce_IBUF,
D => \dd[1]_i_1_n_0\,
Q => \dd_reg_n_0_[1]\,
R => '0'
);
\dd_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ce_IBUF,
D => \dd[2]_i_1_n_0\,
Q => \dd_reg_n_0_[2]\,
R => '0'
);
\ddx[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \dd_reg_n_0_[2]\,
I1 => pos(3),
I2 => \ddx_reg_n_0_[3]\,
O => \ddx[0]_i_1_n_0\
);
\ddx[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \dd_reg_n_0_[1]\,
I1 => pos(3),
I2 => \ddx_reg_n_0_[0]\,
O => \ddx[1]_i_1_n_0\
);
\ddx[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \dd_reg_n_0_[0]\,
I1 => pos(3),
I2 => \ddx_reg_n_0_[1]\,
O => \ddx[2]_i_1_n_0\
);
\ddx[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => ce_IBUF,
I1 => rst_IBUF,
I2 => busy_reg_n_0,
O => ddx
);
\ddx[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => a_IBUF(0),
I1 => pos(3),
I2 => \ddx_reg_n_0_[2]\,
O => \ddx[3]_i_2_n_0\
);
\ddx_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ddx,
D => \ddx[0]_i_1_n_0\,
Q => \ddx_reg_n_0_[0]\,
R => '0'
);
\ddx_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ddx,
D => \ddx[1]_i_1_n_0\,
Q => \ddx_reg_n_0_[1]\,
R => '0'
);
\ddx_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ddx,
D => \ddx[2]_i_1_n_0\,
Q => \ddx_reg_n_0_[2]\,
R => '0'
);
\ddx_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ddx,
D => \ddx[3]_i_2_n_0\,
Q => \ddx_reg_n_0_[3]\,
R => '0'
);
\pos[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEA"
)
port map (
I0 => rst_IBUF,
I1 => pos(3),
I2 => busy_reg_n_0,
I3 => tdo_OBUF,
O => \pos[0]_i_1_n_0\
);
\pos[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00504444"
)
port map (
I0 => rst_IBUF,
I1 => pos(1),
I2 => tdo_OBUF,
I3 => pos(3),
I4 => busy_reg_n_0,
O => \pos[1]_i_1_n_0\
);
\pos[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00504444"
)
port map (
I0 => rst_IBUF,
I1 => pos(2),
I2 => pos(1),
I3 => pos(3),
I4 => busy_reg_n_0,
O => \pos[2]_i_1_n_0\
);
\pos[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0450"
)
port map (
I0 => rst_IBUF,
I1 => pos(2),
I2 => pos(3),
I3 => busy_reg_n_0,
O => \pos[3]_i_1_n_0\
);
\pos_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_IBUF_BUFG,
CE => ce_IBUF,
D => \pos[0]_i_1_n_0\,
Q => tdo_OBUF,
S => '0'
);
\pos_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ce_IBUF,
D => \pos[1]_i_1_n_0\,
Q => pos(1),
R => '0'
);
\pos_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ce_IBUF,
D => \pos[2]_i_1_n_0\,
Q => pos(2),
R => '0'
);
\pos_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_IBUF_BUFG,
CE => ce_IBUF,
D => \pos[3]_i_1_n_0\,
Q => pos(3),
R => '0'
);
rst_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => rst,
O => rst_IBUF
);
tdo_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => tdo_OBUF,
O => tdo
);
\y_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => y_OBUF(0),
O => y(0)
);
\y_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => y_OBUF(1),
O => y(1)
);
\y_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => y_OBUF(2),
O => y(2)
);
\y_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => y_OBUF(3),
O => y(3)
);
\yi[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => busy_reg_n_0,
I1 => a_IBUF(0),
O => \yi[0]_i_1_n_0\
);
\yi[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => \ddx_reg_n_0_[3]\,
I1 => busy_reg_n_0,
I2 => a_IBUF(0),
O => \yi[2]_i_1_n_0\
);
\yi[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A888"
)
port map (
I0 => ce_IBUF,
I1 => rst_IBUF,
I2 => busy_reg_n_0,
I3 => pos(3),
O => \yi[3]_i_1_n_0\
);
\yi[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B0"
)
port map (
I0 => busy_reg_n_0,
I1 => a_IBUF(0),
I2 => ce_IBUF,
O => \yi[3]_i_2_n_0\
);
\yi[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \ddx_reg_n_0_[3]\,
I1 => busy_reg_n_0,
I2 => a_IBUF(0),
O => \yi[3]_i_3_n_0\
);
\yi_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_IBUF_BUFG,
CE => \yi[3]_i_2_n_0\,
D => \yi[0]_i_1_n_0\,
Q => y_OBUF(0),
S => \yi[3]_i_1_n_0\
);
\yi_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_IBUF_BUFG,
CE => \yi[3]_i_2_n_0\,
D => a_IBUF(0),
Q => y_OBUF(1),
S => \yi[3]_i_1_n_0\
);
\yi_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_IBUF_BUFG,
CE => \yi[3]_i_2_n_0\,
D => \yi[2]_i_1_n_0\,
Q => y_OBUF(2),
S => \yi[3]_i_1_n_0\
);
\yi_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_IBUF_BUFG,
CE => \yi[3]_i_2_n_0\,
D => \yi[3]_i_3_n_0\,
Q => y_OBUF(3),
S => \yi[3]_i_1_n_0\
);
end STRUCTURE;