SS 2018 Microelectronics Problems

SS 2018 Problem 1: Chip area and cost

1. How big is a 1GBit chip in 70nm technology?
2. How many chips fit on a wafer with 200mm diameter?
3. How many good chips do you get with 70% yield?
4. What is the defect density for this yield?

SS 2018 Problem 2: VHDL

entity ThisCircuit is port (
        INSIGNAL : in std_logic_vector (3 downto 0);    
        OUTSIGNAL: out std_logic );                                        
end ThisCircuit;
 
architecture ThisCircuit_BEHAVE of ThisCircuit is
signal  a: std_logic;
begin
 a <= INSIGNAL(2) or INSIGNAL(1) ;
 OUTSIGNAL <= INSIGNAL(3) and  a and INSIGNAL(0);
end ThisCircuit_BEHAVE;

1. Draw a schematic described by this VHDL code.
2. Make a truth table of this circuit?
3. How many vectors do you need to test the circuit?

SS 2018 Problem 3: Circuit and Layout Analysis

Calculate the input capacitance of the circuit on the right. The transistor has minimum length in 1µm technology. Technology Rn Rp Scale factor Cox=C'oxWL·(scale)2 1µm (long-channel) 15kL/W 15kL/W 1µm (1.75fF)·WL Calculate the contact resistance of the drain and source contacts, if a single contact has a resistance of 10Ω. A capacitance of 50pF is connected to the output. Calculate the propagation delays and rise and fall time of the output.

SS 2018 Problem 4: Truth table AOI circuit

Make a truth table for the circuit on the right. How do you have to resize the transistors for equal delay to an inverter with a PFET W/L of 12/2 and NFET W/L of 6/2? Give a boolean equation for the circuit.

SS 2018 Problem 5: Circuit

SS 2018 Problem 6: SPICE

*** TOP LEVEL CELL:
Mnmos@0 y a 0 0 N L=0.1U W=0.4U
Mnmos@1 y b 0 0 N L=0.1U W=0.4U
Mpmos@0 net@9 b y vdd P L=0.1U W=0.8U
Mpmos@1 vdd a net@9 vdd P L=0.1U W=0.8U
VD1 vdd 0 DC 1.2
Va a 0 PULSE(0 1.2 5n 1n 1n 4n 10n 20)
Vb b 0 PULSE(0 1.2 12.5n 1n 1n 9n 20n 20)
.include cmosedu_models.txt
.tran 0 25n 0 0.01n
.END

1. Draw a schematic of this circuit?
2. What is the operating voltage?
3. Draw a timing diagram of the signals a, b and y.
4. Why do you need the file cmosedu_models.txt?

SS 2019 HKE Examination Microelectronics

SS 2019 1. Problem: Manufacturing

1. What is the total yield and the relative functional yield? (2 points)
2. Calculate the defect density. (2 points)
3. What would be the total yield, if the chips would have half the area? (2 points)

SS 2019 2. Problem: Circuit properties

1. Calculate the minimum and maximum delay of this circuit from A to Y.(8 points)
2. What is the minimum and maximum voltage of node B? (2 points)
3. What is the maximum current of Mpmos0? (2 points)

SS 2019 3. Problem: layout and parasitics

A top view of a metal line in a 50nm process running from A to B is shown crossing a polysilicon line, which runs from left to right. The metal sheet resistance is Rsquare = 0.2 Ω/square. Plate capacitance is 40 aF/µm2 and fringe capacitance is 90 aF/µm. 1. Calculate the capacitance between the metal line (blue) and the polysilicon line (yellow).(3 points) 2. Calculate the resistance from A to B? (1 points) 3. Calculate the voltage drop on the line if a current of 30µA is flowing. (1 point) 4. Draw a cross section from points C to D (4 points)

C = C_pl · 21 · 50 nm · 50 nm + C_fr · 36 · 50 nm
C = 40 aFµm^-2 · 21 · 50 nm · 50 nm + 90 aFµm^-1 · 36 · 50 nm = 2.1 aF + 162aF = 164 aF

R = R_square · 15 = 3 Ω

V = I · 3 Ω = 90 µV

SS 2019 4. Problem

Make a truth table for the following circuit: (4 points)  C   B   A   Y                          Draw a transistor schematic with the estimated W/L ratio of the transistors. (6 points) Each contact has a resistance of 20Ω. What is the minimum and maximum contact resistance of the source drain contacts of the transistors? (3 points) Draw a cross section along the line from A to B (5 points)

SS 2019 5. Problem: Circuit Analysis

SS 2019 6. Problem: SPICE netlist

* Testcell
Mnmos1 0 Y 0 0 NX L=0.1U W=2U
Mpmos1 Vdd Y Vdd Vdd PY L=0.1U W=3U
Mnmos0 Y Vdd A 0 NX L=0.5U W=4.0U
V1 A 0 SINE(0.5 0.5 50k) AC 1
VD1 vdd 0 DC 0.9
.include cmosedu_models.txt
.ac dec 10 100k 1G
.backanno
.end	

SS 2019 7. Problem

SS 2019 8. Problem: VHDL

entity Amp_test is port(Vin: in BIT; Vout: out BIT);
  end Amp_test;

architecture Amp_test_BODY of Amp_test is
  component inv_1x1 port(a: in BIT; y: out BIT);
    end component;
  component tgr_1x1 port(x: in BIT; y: out BIT);
    end component;
begin
  inv_1x1_0: inv_1x1 port map(net_0, Vout);
  tgr_1x1_1: tgr_1x1 port map(Vin, net_0);
  tgr_1x1_2: tgr_1x1 port map(Vout, gnd);
  tgr_1x1_3: tgr_1x1 port map(Vout, vdd);
end Amp_test_BODY;

SS 2020 HKE Examination Microelectronics

SS 2020 Problem 1

____ SRAM ____ DRAM ____ Flash

SS 2020 Problem 2

1. Why are design rules needed? (2 points)
2. Draw the schematic of the layout below. Mark all design violations in the layout. (5 points)
3. What is the width and the length of the transistors. The smallest feature size in this process is 0.5 µm. (1 point)

Problem 3

SS 2020 Problem 4:

1. Calculate the delay and rise and fall time of the output for a rising and falling output using the following properties. (6 points)
2. Calculate the input capacitance of the circuit. (2 points)
3. How would you optimize the circuit? (1 point)

SS 2020 Problem 5:

1. Calculate the resistance of a polysilicon line with length L. (2 points)
2. If the line resistance is too high, what can you do to lower the resistance? (2 points)
3. Calculate the capacitance between the 2 lines. (3 points)

SS 2020 Problem 6:

A B C Y

SS 2020 Problem 7:

SS 2020 Problem 8:

1. Calculate the maximum number of chips with 150mm² area which fit on a 300mm wafer. (3 points)
2. There is 1 defect per 600mm². How many chips will fail? (1 point)
3. During test of all chips 38 chips are bad. What is the yield? What is the fault coverage? (4 points)
4. Is this a good fault coverage? (2 points)
5. What is the difference between a defect and a fault? (2 points)

SS 2021 HKE Examination Microelectronics

SS 2021 Problem 1:

1. How big is the chip in 90nm technology? (2 points)
2. How many chips fit on a wafer with 300mm diameter? (3 points)
3. What defect density do you need to get a yield of 65%? (4 points).
4. How many more good chips do you get with the same defect density using a 70nm technology? (4 points).

SS 2021 Problem 2:

entity ThisCircuit is port ( 
  op : in STD_LOGIC_VECTOR (1 downto 0);
  vin1,vin2 : in STD_LOGIC;
  vout : out STD_LOGIC);
end ThisCircuit;

architecture Behavioral of ThisCircuit is
  signal acc:STD_LOGIC;
begin
  PROCESS (op)
  BEGIN
    CASE op IS 
      WHEN "00" => acc<= '0';
      WHEN "01" => acc<= vin1 or vin2;
      WHEN "10" => acc<= vin1 xor vin2;
      WHEN "11" => acc<= vin1 and vin2;
      WHEN OTHERS => acc<='0';
    END CASE;
  END PROCESS;
  vout <= acc;
end Behavioral;

constant Tp : time := 50 ns;
stim_proc: process
begin 
  op <= "00"; vin1 <='0'; vin2 <='1'; wait for Tp;
  op <= "01"; vin1 <='1'; vin2 <='0'; wait for Tp;
  op <= "10"; vin1 <='0'; vin2 <='0'; wait for Tp;
  op <= "11"; vin1 <='1'; vin2 <='0'; wait for Tp;
  op <= "11"; vin1 <='1'; vin2 <='1'; wait for Tp;
end process;

SS 2021 Problem 3: Test

1. Why do you have to test integrated circuits? (2 points)
2. Give an electrical model for a transition delay fault. (2 points)
3. Give an electrical model for a stuck at ´1` fault. (2 points)
4. What is a scan chain? What signals do you need and what is their purpose? How does a scan chain operate? What is the benefit and drawback of a scan chain? (12 points)

SS 2021 Problem 4:

1. Calculate the minimum and maximum propagation delay for the circuit below, when a 10pF Capacitance is connected to the output. (4 points)
2. Calculate the maximum input capacitance of the circuit. (3 points)
3. What would be the W/L ratio of the transistors to optimize the circuit for minimum power consumption? Why is the power consumption lower? (4 points)
4. What would be the W/L ratio of the transistors to optimize the circuit to have a delay equal to an inverter with a NFET W/L 2/2 and PFET W/L 6/2? (4 points)

SS 2021 Problem 5:

1. Calculate the capacitance between the 2 metal lines.(2 points)
2. How could you change the capacitance between the lines in a given CMOS process? (5 points)
3. Calculate the voltage drop on the line if a current of 10µA is flowing. ( 2 points)

SS 2021 Problem 6:

1. Make a truth table for the following circuit.(4 points)
   

   A B C Y

2. Draw a transistor schematic.(4 points)
3. Give the boolean equation? (3 points)

SS 2021 Problem 7: Microprocessor

1. What are the three states of a instruction decoder of a microprocessor? What happens during these states? (6 points)
2.  Describe step by step what happens with the registers IR, PC, ACC and Z during the execution of the program. (12 points)

SS 2021 Problem 8: SPICE

*** SUBCIRCUIT Inv_1x FROM CELL Inv_1x{lay}
.SUBCKT Inv_1x VDD VSS Vin Vout
Mnmos@0 VSS Vin Vout gnd N_1u L=1U W=6U 
Mpmos@1 VDD Vin Vout vdd P_1u L=1U W=12U
.ENDS Inv_1x
*** TOP LEVEL CELL: Test_dc_inv{lay}
XInv_1x@0 VDD 0 Vin Vout Inv_1x
XInv_1x@1 VDD 0 Vout Vres Inv_1x
*** SIGNALS
VIN Vin 0 DC 0
VDD_1 VDD 0 DC 2.9
.include cmosedu_models.txt
.dc VIN 0 3.3 10m
.END

1.  What simulation is done with this SPICE code? Describe the circuit, signals and simulation. (5 points)
2.  How many transistors are implemented, what are the dimensions and what is the transistor model name? (5 point)
3. What is the operating voltage? (1 point)
4.  Draw v(Vout),V(Vres) versus v(Vin) of this circuit. Label the axis and important measurement points. Discuss the curve. The PFET has V_tp=-0.8V and the NFET V_tn=0.8V. I_DSN=2*I_DSP. (11 points)

SS 2021 Problem 9:

SS 2022 HKE Examination Microelectronics

SS 2022 1. Problem Manufacturing:

1. What are the contact yield, the DC yield and the total yield? (6 points)
2. What is the defect density? (2 points)
3. How many transistors are realized on one chip? (2 points)
4. What can go wrong during manufacturing of integrated circuits? (6 points)

SS 2022 2. Problem Output voltage:

1. Give the maximum voltages at the points OUT1, OUT2 and Out for an operating voltage of 1V. (4 points)
2. Calculate the delay from In1 to OUT1 through M1. (3 points)
3. Make a truth table. ( 4 points)

SS 2022 3. Problem layout and parasitic:

A top view of a metal line in a 90 nm process running from A to B is shown crossing a polysilicon line, which runs from left to right. The metal sheet resistance is Rsquare = 0.4 Ω / square. The lines are isolated with 150 nm oxide. (ε0 = 88 fF/cm, εSiO2 = 4) Calculate the capacitance between metal line (blue) and the polysilicon line (yellow).(2 points) Calculate the resistance from A to B. (2 points) Draw a cross section from points C to D. (4 points)

1. \( C = \epsilon \frac{A}{d} = \epsilon_{0} \cdot \epsilon_{SiO_{2}} \frac{ 90 nm \cdot 90nm \cdot 10}{150 nm} = 88 fF \cdot 10^{-7}nm^{-1} \cdot 4 \frac{ 90 nm \cdot 90nm \cdot 10}{150 nm} = 0.019 fF \)(2)
2. \( R= ( 1 + 0.75 + 6) R_{square} = 7.75 \cdot 0.4 \Omega = 3.1 \Omega \) (2)
3. V = I \middot R = 12 µ V

SS 2022 4. Problem

Make a truth table for the following cicuit: (4 points)  D   C   B   A   Y                                                  Draw a transistor schematic with te W/L ratio of the transistors. (6 points) Give the Boolean equation. (3 points) Each contact has a resistance of 20 Ω. What is the minimum and maximum contact resistance of the source drain contacts of the transistors? (3 points) Draw a cross section along the line from A to B (5 points)

\( Y = /((A \cdot B) + (C \cdot /D) ) \)      (3)
2 contacts in parallel R_max = 10 \Omega      (1)
7 contacts in parallel R_min = Rcontact / 7 = 2.86 \Omega      (2)
(5)
Each error -1.

SS 2022 5. Problem: Circuit analysis

SS 2022 6. Problem: SPICE netlist

* Testcell 
M1 N001 N002 0 N003 NMx l=0.25u w=750n 
R1 VDD N001 10k 
C1 N001 0 20f 
V1 N002 0 DC 0 
V2 VDD 0 DC 2 
V3 N003 0 DC 0 
M2 N001 N002 0 N003 NMy l=0.5u w=750n 
.dc V1 0 2 0.1 V3 0 -1 -1 
.end 
 

1. What simulation is done with this SPICE code? Make a schematic, describe the circuit, signals and simulation. (5 points)
2. How many transistors are implemented, what are the dimensions and what is the transistor model name? (5 point)
3. What is the operating voltage? (1 point)
4. Draw I(R1) versus V(V1) of this circuit for this simulation (Vthn0=0.5V). Label the axis and important measurement points. Discuss the curve. (5 points)

A DC simulation V1 is varied from 0 to 2 V with 0.1V step. (1)
V3 is varied from 0 to -1V with -1V step. (1)
V2 is constant at 2V.
(3)
2 Transistors are implemented (1)
width=750nm (1)
length 250nm M1 (1)
and 500nm M2 (1),
model name:NMx (1)
3. Operating voltage 2V

x.-axis: V1 gate source voltage
y-axis: drain source current
Transfer characteristic (1)
At V1=0.5V current starts to flow (1)
At high voltages is limited by resistor, linear region. (1)
If well is biased the threshold voltage changes. (1)
Vth will get larger. (1)

SS 2022 7. Problem

1. How do you cope with complexity? (4 points)
2. What is a floorplan? (2 points)
3. What are standard cells? What properties do they have? (4 points)
4. What is design verification? (2 points)
5. What is a wired AND fault model? (3 points)

SS 2022 8. Problem

A   B   C   D   Z   0  0 0 0 1  0  0 0 1 1  0  0 1 0 1  0  0 1 1 1  0  1 0 0 1  0  1 0 1 1  0  1 1 0 0  0  1 1 1 0  1  0 0 0 1  1  0 0 1 0  1  0 1 0 1  1  0 1 1 0  1  1 0 0 1  1  1 0 1 0  1  1 1 0 0  1  1 1 1 0

SS 2023 HKE Examination Microelectronics

SS 2023 1. Problem Manufacturing:

SS 2023 2. Problem Circuit properties:

SS 2023 3. Problem Layout and parasitic:

A top view of a metal line in a 50nm process running from A to B is shown crossing a polysilicon line, which runs from left to right. The metal sheet resistance is Rsquare=0.6Ω/square. The lines are isolated with 80nm oxide. (ε0= 88 fF/cm, εSiO2 = 4) 1. Calculate the capacitance between the metal line (blue) and the polysilicon line (yellow).(2 points) 2. Calculate the resistance from A to B? (2 points) 3. Calculate the voltage drop on the line if a current of 30µA is flowing. (2 points) 4. Draw a cross section from points C to D (4 points)

SS 2023 4. Problem:

Make a truth table for the following circuit: (4 points)  D   A   B   C                                  Draw a transistor schematic with the W/L ratio of the transistors. (6 points) Each contact has a resistance of 20Ω. What is the minimum and maximum contact resistance of the source drain contacts of the transistors? (3 points) Draw a cross section along the line from A to B (5 points)

SS 2023 5. Problem: Circuit Analysis

SS 2023 6. Problem: SPICE netlist

* Testcell
Mnmos0 N001 A 0 0 N L=0.1U W=0.4U
Mpmos0 N001 A Vdd Vdd P L=0.1U W=0.8U
Mnmos1 Y N001 0 0 N L=0.1U W=1.6U
Mpmos1 Y N001 Vdd Vdd P L=0.1U W=3.2U
C1 Y 0 100fF
VD1 vdd 0 DC 1.2
Va a 0 PULSE(0 1.2 5n 1n 1n 4n 10n 20)
.include cmosedu_models.txt
.tran 0 25n 0 0.01n

SS 2023 7. Problem:

SS 2023 Problem 8 VHDL:

entity ThisCircuit1 is port ( 
  clk: in STD_LOGIC;
  a: in STD_LOGIC_VECTOR (1 downto 0);
  b : in STD_LOGIC;
  y: out STD_LOGIC);
end ThisCircuit1;

architecture Behavioral of ThisCircuit1 is
  signal xy:STD_LOGIC;
begin
  PROCESS (clk)
  BEGIN
    if (clk='1' and clk'event) then
      CASE a IS 
        WHEN "00" => xy<=xy and b;
        WHEN "01" => xy<=a(0) or b;
        WHEN "10" => xy<=b and xy;
        WHEN "11" => xy<=a(1) and b;
        WHEN OTHERS => xy<='0';
      END CASE;
    end if;
  END PROCESS;
  y <= xy or b;
end Behavioral;

   constant Tp : time := 10 ns;
BEGIN
  clk_process :process
  begin
    clk <= '0'; wait for Tp/2;
    clk <= '1'; wait for Tp/2;
  end process;
  stim_proc: process
  begin 
    a <= "11"; b <='1'; wait for Tp;
    a <= "10"; b <='0'; wait for 2*Tp;
    a <= "00"; b <='1'; wait for Tp;
    a <= "01"; b <='0'; wait for Tp;
    a <= "11"; b <='0'; wait for Tp;
  end process;;

Questions: