Schaltungstechnik

16 Spannungsregler

Längsregler

Prof. Dr. Jörg Vollrath

15 Rauschen

Video der 16. Vorlesung 18.5.2021

Länge: 1:02:43

0:2:16 5.1 Power overview

0:4:26 5.2 Power converters

0:6:2 5.3 Need for converters

0:8:18 Load Regulation

0:11:30 Line Regulation

0:13:55 Wirkungsgrad, Efficiency

0:14:39 5.4 DC Power Distribution PC

0:19:20 5.5 Types of Converters

0:24:20 DRAM power grid

0:29:30 Power on sequence

0:35:50 Linear regler, standard and LDO

0:37:0 5.7 Pros and Cons

0:41:4 Beispiel Längsregler (Linearregler)

0:49:10 Diskussion Ergebnis

0:52:35 Welligkeit, ripple

0:55:0 5.9 Board space

0:57:44 5.11 PFET as pass device

1:1:40 5.13 Freilaufdiode

1:2:44 5.15 Stabilität

1:5:20 LTSPICE Praktikumsschaltung

1:11:20 Laständerung am Ausgang

1:13:28 Load regulation LoR = 30mV/300mA = 0.1 Ohm

1:15:55 Spannungsverlauf bei Laständerung

1:18:40 Stabilität

Start

Power

5.1 Power Overview
5.2 Power Converters
5.3 Load Regulation, Line Regulation

Unit 5, 1-21

Begriffe

Quelleninnenwiderstand
Statisch
Line Regulation (LiR):
$LiR = \frac{\delta V_{out}}{ \delta V_{in}}$
Power Efficiency (Eta):
$\eta = \frac{V_{out} \cdot I_{out}}{V_{in} \cdot I_{in}}$
Lastausregelung (Load regulation, LoR)
$LoR = \frac{\delta V_{out}}{ \delta I_{out}}$
Innenwiderstand
Dynamisch
Welligkeit

Ideal power conversion:
Vin · Iin = Vout · Iout

Example: Vin = 2 V, Vout = 4 V, Iout = 100 mA
Calculate Iin.
Iin = 200 mA

Power grid: DRAM example

5.4 DC/DC Power Distribution

There are separate power supply pins for the data input and outputs (IO).
The number of power pins is proportional to the number of IOs.
There are separate grids for digital and analog circuits.
Horizontal and vertical lines are connected to a grid and provide power.

The block diagram shows different voltages in different colors in different areas.
Voltage pumps and regulators are shown in grey.
A bandgap reference circuit provides temperature and voltage independent voltages.

Power on sequence: DRAM

DRAM internal voltages and power on sequence.

A low array voltage is used to save power.
A negative back bias is needed reducing memory cell leakage current.
A high voltage V_pp gives the select transistor overdrive to store the full V_blh level in the memory cell.
Vint is optimized for speed and to be able to drive the IOs.
A high current peak, when power is turned on, has to be avoided.
All capacitances will be charged up at power up.

Linearregler

5.5 Types of Converters
5.6 Linear Regulators
5.7 Pros and Cons of Linear Regulators
5.8 Linear Regulators efficiency and ripple
5.9 Linear Regulators board space

Unit 5, 1-21

P3, V3: Linearregler

5.10 Linear regulator inside
5.11 PFET

LinearV3.asc

Version 4
SHEET 1 2164 680
WIRE 128 -16 32 -16
WIRE 272 -16 128 -16
WIRE 400 -16 272 -16
WIRE 448 -16 400 -16
WIRE 576 -16 544 -16
WIRE 624 -16 576 -16
WIRE 640 -16 624 -16
WIRE 752 -16 720 -16
WIRE 880 -16 752 -16
WIRE 880 16 880 -16
WIRE 272 32 272 -16
WIRE 624 32 624 -16
WIRE 752 64 752 -16
WIRE 32 96 32 -16
WIRE 128 112 128 -16
WIRE 400 112 400 -16
WIRE 272 128 272 112
WIRE 320 128 272 128
WIRE 368 128 320 128
WIRE 624 128 624 112
WIRE 624 128 544 128
WIRE 272 144 272 128
WIRE 464 144 464 32
WIRE 464 144 432 144
WIRE 496 144 464 144
WIRE 624 144 624 128
WIRE 880 144 880 96
WIRE 368 160 336 160
WIRE 400 192 400 176
WIRE 336 240 336 160
WIRE 480 240 336 240
WIRE 544 240 544 128
WIRE 544 240 480 240
WIRE 880 240 880 224
WIRE 944 240 880 240
WIRE 32 256 32 176
WIRE 128 256 128 176
WIRE 272 256 272 208
WIRE 624 256 624 224
WIRE 752 256 752 128
WIRE 880 256 880 240
WIRE 880 352 880 336
FLAG 32 256 0
FLAG 128 256 0
FLAG 272 256 0
FLAG 400 192 0
FLAG 624 256 0
FLAG 752 256 0
FLAG 880 -16 Vout
FLAG 128 -16 Vin
FLAG 320 128 Vref
FLAG 480 240 VFB
FLAG 496 144 VG
FLAG 880 352 0
FLAG 576 -16 Vx
FLAG 944 240 Vload
SYMBOL voltage 32 80 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 112 112 R0
SYMATTR InstName C1
SYMATTR Value 10�
SYMBOL zener 288 208 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N750X
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 256 16 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL AD820B 400 80 R0
WINDOW 0 17 33 Left 2
SYMATTR InstName U1
SYMATTR Value AD820B
SYMBOL pmos 544 32 M270
SYMATTR InstName MP1
SYMATTR Value IRF9530
SYMBOL res 608 16 R0
SYMATTR InstName R2
SYMATTR Value 2.2k
SYMBOL res 608 128 R0
SYMATTR InstName R3
SYMATTR Value 6.8k
SYMBOL cap 736 64 R0
SYMATTR InstName C2
SYMATTR Value 10�
SYMBOL res 864 0 R0
SYMATTR InstName R4
SYMATTR Value 30
SYMBOL res 864 128 R0
SYMATTR InstName R5
SYMATTR Value 3
SYMBOL voltage 880 240 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.26 1m 1u 1u 9m 20m)
SYMBOL res 736 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 0.1
TEXT 24 -216 Left 2 !.model IRF9530  PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0\n+Tox=100n Uo=300 Phi=.6 Rs=.1576 Kp=10.57u W=1.4 L=2u Vto=-3.745\n+ Rd=66.13m Rds=444.4K Cbd=1.249n Pb=.8 Mj=.5 Fc=.5 Cgso=1.578n\n+ Cgdo=115.5p Rg=3.519 Is=2.938E-18 N=2 Tt=290n)
TEXT 16 312 Left 2 !.model 1N750X D(Is=.88f Rs=.25 Cjo=175p M=.55 nbv=1.7 bv=2.5 \n+Vj=.75 Isr=1.86n Nr=2 Ibv=20.245m Ibvl=1.96m Nbvl=15 Tbv1=-21.3u \n+Vpk=2.5 mfg=OnSemi type=Zener)
TEXT 24 -88 Left 2 !;op
TEXT 104 -88 Left 2 !.include AD820B.spi
TEXT 16 -56 Left 2 !;dc V1 6 12 1
TEXT 312 264 Left 2 !*VREF Vref 0 DC 2.5
TEXT 192 -48 Left 2 !.tran 60m
TEXT 624 -96 Left 2 !;ac dec 10 1 1G
TEXT 8 400 Left 2 ;Efficiency: -(V(vout)*I(R4))/(V(vin)*I(V1))

Line Regulation (LiR): I = 100 mA, R = 33 Ω

$LiR = \frac{\delta V_{out}}{ \delta V_{in}} = \frac{3.26 - 3.18}{ 12 - 6 } = 1.3 \%$

Power Efficiency (Eta):

$\eta = \frac{V_{out} \cdot I_{out}}{V_{in} \cdot I_{in}}$

Lastausregelung (Load regulation, LoR)

$LoR = \frac{\delta V_{out}}{ \delta I_{out}}$
dI = 100 mA
dV_out = 3.257 V - 3.247 V = 10 mV
LoR = 0.1 Ω

R6 zwischen Vx und Vout verhindert Schwingung.

Zusammenfassung und nächste Vorlesung

Typische Versorgungsspannungen in Systemen
Spannungsversorgungsnetzwerk
Line Regulation, Load Regulation
Wirkungsgrad, power efficiency
Linearregler
Simulation und Rechnung

Nächstes Mal

17 Schaltregler

2021 Schaltungstechnik 16 Laengsregler Prof. Dr. Joerg Vollrath