Hochschule Kempten      
Fakultät Elektrotechnik      
Interface Electronics       Fachgebiet Elektronik, Prof. Vollrath      

Interface Electronics

14 Figure of Merit

Prof. Dr. Jörg Vollrath

13 Sigma Delta ADC

Review and Overview

Data converter performance parameters

ISSC 2008 [1]VLSI 2012 [2] VLSI 2013 [3]ISSC 2014 [4]
Technology [nm]9040 32 SOI40 LP
Resolution56 67
Power supply [V]11.1 0.851.1
Sampling Frequency [GS/s]1.753 52.2
Power Consumption [mW]2.211 8.527.4
SNDR @Nyquist [dB]27.633.1 30.937.4
FoMw [fJ/conv step]64.599.3 59.4210
FoMs [dB]143.5144.4 145.6143.3
Core area [mm2]0.01650.021 0.020.052
CalibrationOff chipForeground Off chipNo need

[1] B. Verbruggen, et al., “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS,” ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 2008.
[2] Y.-S Shu, “A 6b 3GS/s 11mW Fully Dynamic ADC in 40nm CMOS with Reduced Number of comparators,” Symp. VLSI Circuits, pp. 26-27, June 2012.VLSI 2012
[3] V. H. -C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI,” Symp. VLSI Circuits , pp. 264-265, June 2013.
[4] M. Miyahara, et. al., "22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers," 2014 ISSCC, San Francisco, CA, 2014, pp. 388-389.

Data converter performance parameters


Video: https://www.youtube.com/watch?v=dlD0Jz3d594
A figure of merit (FoM) is a useful tool for comparing the conversion efficiency of A/D converters. This presentation reviews the make-up and composition of the most popular FoMs quantifying the tradeoff between ADC speed, resolution and power dissipation. In addition, it investigates the pertaining asymptotes and trends over time. The obtained information allows us to quantify past progress rates and lets us speculate about the future.

ADC Figure of Merit


\( FOM_{1} = \frac{Power}{f_{S} \cdot 2^{ENOB}} [fJ/conversion step] \)

\( ENOB = \frac{SNDR-1.76}{6.02} \)

Ref: R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999


\( FOM_{2} = SNR + 10log\left( \frac{f_{S}}{2 P}\right) [dB]\)

R. Schreier and G.C.Termes, Understanding Delta-Sigma Data-Converters, Wiley 2005

\( FOM_{3} = SNDR + 10log\frac{f_{S}}{2 Power} [dB]\)

A.M.A. Ali et al., "A 16-bit 250MS/s IF Sampling Pipelined ADC with background calibration, JSSC, Dec2010


Fundamental Limit

Class-B Amplifier, sample and hold C, Brickwall LPF at fsample/2

\( SNR = \frac{\frac{1}{2} \left( \frac{V_{FS}}{2}\right)^2 }{\frac{kT}{C}} \frac{f_S}{f_{snyq}} = \frac{1}{8} \frac{C}{kT} V_{FS}^{2} \frac{f_S}{f_{snyq}} \)
Pmin = I · V = Q · fsample · VDD = C · VFS · fS · VFS


\( E_{min} = \frac{P_{min}}{f_{synyq}} = 8 k T \cdot SNR \)
Energy over SNR, energy per bit.

Ref: Hosticka, Proc. IEEE 1985; Vitoz, ISCAS 1990

\( FOM_{2} = SNR + 10log\left( \frac{f_{S}}{2 P}\right) = SNR + 10log\left( \frac{1}{E_{min}}\right) = 10 log\left( \frac{1}{8kT}\right) = 198 dB\)

DAC ADC Measurement




Offset Error:

Gain Error:


DAC Bits ADC Bits NOffset Error Gain ErrorComment
3 3 1 0 0Same number of Bits and no error
3 5 1 2 -20%DAC is tested by ADC and shows a limited output range
5 4 1 2 -20%ADC is tested by DAC and shows a limited output range

ADC and DAC same number of bits:

Total errors bigger than 1 LSB can be detected.
Offset and gain errors can lead to a reduced number of output codes.
It is not clear if ADC or DAC has errors.

ADC has more bits than DAC:

Only DAC is tested
INL, DNL errors of 2BDAC/BADC · LSB can be detected.
Offset and gain error can lead to a limited output range.

ADC has less bits than DAC:

Only ADC is tested.
INL, DNL errors of 2BADC/BDAC · LSB can be detected.
A range of DAC codes gives the same ADC output code. This is a histogramm test.

General remarks

Taking multiple measurement points per DAC code can look like a histogram test.
Noise can cause multiple ADC codes per DAC code.
A histogram test averages noise out.
Applying an operational amplifier (Opamp) can increase the resolution of ADC or step size of DAC and adding an offset.
Using a voltage divider enables smaller DAC step sizes.
Characterization can then be done using multiple steps for sub ranges with different offsets.

DAC ADC Test Simulation

DAC X4 provides coarse steps, DAC X2 provides fine steps for ADC test.
For high resolution DAC test The DAC ouput can be amplified and an offset applied and the tested with the ADC.
Another possibility for DAC test would be to build a 2 stage multibit pipeline ADC.

Summary of Interface Electronics


Overview Interface Electronics