This laboratory uses a modified Word file.
Word example report
Make a file name with year, topic, last name, version.
Be prepared to make a presentation.
Save all simulation input files, images, references in subdirectories.
ADC DAC Schematic
The schematic shows a 4-bit ADC DAC simulation set up.
Simulate a ramp test.
V2 in1 0 PULSE()
Make sure the .save V(in1) V(vout) saves vout as last value, to be able to postprocess it.
The simulation generates a file 4Bit_ADC_DAC_pipe.raw with simulated values.
Unfortunately this file is binary coded and timesteps are varying.
Extract the simulated values with
Read Raw File .
You can also calculate INL, DNL with any tool you like.
Document and discuss INL and DNL values.
Simulate a sine signal test.
Extract the simulated values with
Read Raw File .
Calculate FFT, INL, DNL with
FFT webpage and paste the
extracted values from LTSPICE into the input field.
Document and discuss FFT, INL, DNL and SNR values.
How is the input signal generated?
Which circuits are used?
What is the sample frequency?
Display the digital signals!
Calculate INL, DNL!
Please submit via email to joerg.vollrath@hs-kempten.de until 4.11.2024 a
report covering laboratories 1..3.
Please remove in LTSPICE folder the simulation output files .raw.
In LTSPICE select a different folder for the output files:
LTSPICE Tools, Control Panel, Waveforms, Store .raw in a special directory, C:\var\raw
You should zip the folder with a name like: 2019_Group<A..P>0<0,1>
Video Instructions LTSPICE ADC DAC Test Circuit
This video presents the download and run of LTSPICE files.
Search for "Vollrath InEl"
Open LTSPICE presentation.
Go to "Scalable behavioral 4 Bit DAC",
"Scalable behavioral 4 Bit ADC",
"Test for 4 Bit ADC and DAC" slides and download circuits (.asc) and (.asy)
presented to you after clicking on the circuit.
Run the sine simulation and view V(in1),V(out).
Create a pulse voltage source:
V1 in1 0 PULSE(0 1 0 655.36u 655.36u 0 1310.72u)
Run a ramp simulation.
Duration 10:52 min
01:20: : Download schematics for schematics
04:10: : Download symbols for 4Bit_ADC_DAC_pipe.asc, 4Bit_ADC_pipe.asc, 4Bit_DAC_pipe.asc, sample_hold.asc, Switch.asc,WS2011_Prob4.asc
05:00: : Sine input
05:35: : Output signal
06:30: : LTSPICE FFT
07:30: : Ramp
09:35: : Voltage source
Video Instructions LTSPICE INL, DNL FFT Analysis
This video presents the analysis of LTSPICE simulation files.
Run the ADC DAC test simulation in LTSPICE with a ramp.
Extract the simulated values with
Read Raw File .
Use analysis buttons to:
Show extracted values
Map values to integers
DAC INL, DNL analysis
ADC histogram analysis
Run the ADC DAC test simulation in LTSPICE with a sine signal.
Extract the simulated values with
Read Raw File .
Use the integer values for a FFT analysis.
Duration 13:48 min
00:28: : Read LTSPICE raw data
04:15: : Start time 0, Stop time 655.36E-6, Time step: 40.96E-6
04:58: : First data
05:50: : Map to integer
06:25: : DNL INL graph
07:13: : Histogram with smaller step size 5.12E-6
08:10: : Map to integer
08:42: : ADC histogram analysis
09:20: : Simulate sine
09:50: : Read data values
11:05: : Histogramm test
11:40: : Copy values
12:00: : ADC FFT Javascript, Fill input data field, read integer values
12:50: : SNR 11.87-(-13.89) dB = 25.76 dB ENOB = (15.76-1.76)/6.02 = 4
13:16: : Sine histogram INL and DNL
Simulation R2R DAC
The schematic shows a 4-bit R2R DAC.
We will use it in the ADC DAC simulation to see some errors.
Create a symbol and hook it up to the ADC DAC test circuit from last week.
Modify the resistance values. For example 1.5k, 2.5k, 1.3k, 1.7k.
Simulate a ramp test.
Extract the simulated values with
Read Raw File .
Calculate INL, DNL with any tool.
Document and discuss INL and DNL values.
Simulate a sine signal test.
Extract the simulated values with
Read Raw File .
Calculate FFT, INL, DNL with
FFT webpage and paste the
extracted values from LTSPICE into the input field.
Document and discuss FFT, INL, DNL and SNR values.
Duration 6:34 min
00:34: : Include R2R DAC
01:52: : Simulate real R2R DAC
02:23: : Modify R values: R6 1.3k, R9 1.5k
03:16: : Read, mapto integer, copy values to FFT, process
04:29: : SNR 12.09-(-6.75) dB = 18.84 dB
04:55: : Ramp test
05:28: : Step 40.96E-6
06:07: : INL and DNL with error
Video Instructions LTSPICE .Measurement
This video presents the analysis of LTSPICE simulation files with
a .measure statement.
Run the ADC DAC test simulation in LTSPICE with a ramp.
Insert SPICE directive:
.meas trans OUT00 FIND V(vout) AT=81.92us
After simulation "View","SPICE Error log" will show the result.
Multiple measurement statements can be placed into a file.
After simulation "File","Execute .MEAS script" generates the results.
A 10-bit data converter should have about 16384 measurement values.
Data extraction can be difficult and quite time consuming.
Duration 5:55 min
00:44: Measurement statement
01:35: First measurement statement: .meas trans OUT00 FIND V(vout) at t=20.48u
05:20: .meas script