Interface ElectronicsLaboratory 05: Pipeline ADCProf. Jörg Vollrath |
Overview
- Circuit
- LTSPICE simulation: Ramp, sine
- FFT, INL, DNL, SNR
- Summary
This is a laboratory to simulate (, build and measure) a pipeline ADC.
Pipeline ADC circuit: Overview
Opamp3.asc Opamp3.asy SwitchX.asc SwitchX.asy Shift8.asc Shift8.asy INVy.asc INVy.asy 4Bit_DAC_pipe.asc 4Bit_DAC_pipe.asy Shift.asc Shift.asy XSH.asc XSH.asy Comp3.asc Comp3.asy
Version 4 SHEET 1 2224 828 WIRE 368 -96 -128 -96 WIRE 976 -96 368 -96 WIRE 1536 -96 1488 -96 WIRE 1552 -96 1536 -96 WIRE -80 -80 -144 -80 WIRE 1376 -64 1328 -64 WIRE 1536 -64 1376 -64 WIRE 1760 -64 1760 -80 WIRE -128 -32 -128 -96 WIRE -112 -32 -128 -32 WIRE -16 -32 -48 -32 WIRE 1104 -32 1088 -32 WIRE 1216 -32 1104 -32 WIRE 1376 -32 1328 -32 WIRE 1536 -32 1376 -32 WIRE -80 0 -144 0 WIRE 1104 0 1104 -32 WIRE 1120 0 1104 0 WIRE 1216 0 1184 0 WIRE 1376 0 1328 0 WIRE 1536 0 1376 0 WIRE 1696 0 1664 0 WIRE -80 16 -80 0 WIRE 368 16 336 16 WIRE 448 16 448 -16 WIRE 576 16 528 16 WIRE 1808 16 1760 16 WIRE -224 32 -224 0 WIRE 1104 32 1088 32 WIRE 1216 32 1104 32 WIRE 1376 32 1328 32 WIRE 1536 32 1376 32 WIRE 1760 32 1760 16 WIRE -256 48 -320 48 WIRE -160 64 -192 64 WIRE -112 64 -160 64 WIRE -16 64 -16 -32 WIRE -16 64 -48 64 WIRE 16 64 -16 64 WIRE 48 64 16 64 WIRE 464 64 48 64 WIRE 1104 64 1104 32 WIRE 1120 64 1104 64 WIRE 1216 64 1184 64 WIRE 1376 64 1328 64 WIRE 1408 64 1376 64 WIRE 1536 64 1504 64 WIRE -256 80 -288 80 WIRE 1504 80 1504 64 WIRE 144 96 144 32 WIRE 1104 96 1088 96 WIRE 1216 96 1104 96 WIRE 1376 96 1328 96 WIRE 1392 96 1376 96 WIRE 1536 96 1488 96 WIRE -288 112 -288 80 WIRE -160 112 -160 64 WIRE -160 112 -288 112 WIRE 16 112 16 64 WIRE 112 112 16 112 WIRE -224 128 -224 96 WIRE 208 128 176 128 WIRE 224 128 208 128 WIRE 256 128 224 128 WIRE 336 128 336 16 WIRE 368 128 336 128 WIRE 736 128 672 128 WIRE 1104 128 1104 96 WIRE 1120 128 1104 128 WIRE 1216 128 1184 128 WIRE 1376 128 1328 128 WIRE 1696 128 1696 0 WIRE 1696 128 1504 128 WIRE -16 144 -16 128 WIRE 112 144 80 144 WIRE 736 144 736 128 WIRE 1760 144 1760 112 WIRE 336 160 336 128 WIRE 512 160 512 112 WIRE 1216 160 1088 160 WIRE 1360 160 1328 160 WIRE 464 176 464 64 WIRE 480 176 464 176 WIRE 912 176 912 144 WIRE 1536 176 1488 176 WIRE 576 192 576 16 WIRE 576 192 544 192 WIRE 608 192 608 80 WIRE 608 192 576 192 WIRE 704 192 608 192 WIRE 800 192 768 192 WIRE 816 192 800 192 WIRE 880 192 816 192 WIRE 448 208 448 16 WIRE 480 208 448 208 WIRE 976 208 976 -96 WIRE 976 208 944 208 WIRE 1408 208 1408 64 WIRE 1536 208 1408 208 WIRE 880 224 848 224 WIRE 144 240 144 160 WIRE 144 240 48 240 WIRE 1392 240 1392 96 WIRE 1536 240 1392 240 WIRE 336 256 336 240 WIRE 848 256 848 224 WIRE 976 256 976 208 WIRE 976 256 848 256 WIRE 800 272 800 256 WIRE 912 272 912 240 WIRE 1376 272 1376 128 WIRE 1536 272 1376 272 WIRE 1696 272 1664 272 WIRE 1808 272 1776 272 WIRE 1856 272 1808 272 WIRE 128 304 112 304 WIRE 208 304 208 208 WIRE 240 304 208 304 WIRE 512 304 512 224 WIRE 512 304 432 304 WIRE 1360 304 1360 160 WIRE 1536 304 1360 304 WIRE 1504 336 1504 128 WIRE 1536 336 1504 336 WIRE 1536 368 1488 368 WIRE 1808 368 1808 336 FLAG 144 32 VDDp FLAG 48 240 VDDn FLAG -320 48 In IOPIN -320 48 In FLAG 608 80 Vout IOPIN 608 80 Out FLAG 432 304 VDDn FLAG 512 112 VDDp FLAG 240 304 Dout IOPIN 240 304 Out FLAG 80 144 Vref FLAG 1808 16 Vref FLAG 1760 -80 VDDp FLAG 1760 144 VDDn FLAG -16 144 0 FLAG 800 272 0 FLAG 912 144 VDDp FLAG 912 272 VDDn FLAG -144 0 CLK1 FLAG -144 -80 CLK3 FLAG 672 128 CLK2 FLAG 368 -96 Vres FLAG 48 64 Vinx FLAG 816 192 Voutx FLAG 1088 -32 CLK2 FLAG 1088 32 CLK3 FLAG 1088 96 CLK1 FLAG 1088 160 Dout FLAG 1504 80 0 FLAG 1488 96 VDDp FLAG 1488 368 VDDp FLAG 1488 -96 CLK1 FLAG 1488 176 CLK1 FLAG 1856 272 Vouty FLAG 1376 -64 D0 FLAG 1376 -32 D1 FLAG 1376 0 D2 FLAG 1376 32 D3 FLAG 1376 64 D4 FLAG 1376 96 D5 FLAG 1376 128 D6 FLAG 1360 160 D7 FLAG 1808 368 0 FLAG -224 0 VDDp FLAG -224 128 VDDn FLAG 112 304 VDDp FLAG 336 256 0 FLAG 224 128 Dx FLAG 368 128 Dy SYMBOL res 1744 -80 R0 SYMATTR InstName R1 SYMATTR Value 20k SYMBOL res 1744 16 R0 SYMATTR InstName R2 SYMATTR Value 20k SYMBOL res 544 0 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL Opamp3 512 192 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X1 SYMATTR SpiceLine Aol=1000000 GBW=0.01G SYMBOL cap -32 64 R0 SYMATTR InstName C1 SYMATTR Value 20n SYMBOL cap 784 192 R0 SYMATTR InstName C2 SYMATTR Value 20n SYMBOL Opamp3 912 208 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X6 SYMATTR SpiceLine Aol=100000 GBW=0.01G SYMBOL res 192 112 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res 224 288 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL SwitchX -80 64 R0 SYMATTR InstName X2 SYMBOL SwitchX -80 -32 R0 SYMATTR InstName X4 SYMBOL SwitchX 736 192 R0 SYMATTR InstName X5 SYMBOL res 464 0 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 33 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 120k SYMBOL Shift8 1264 64 R0 SYMATTR InstName X7 SYMBOL INVy 1152 64 R0 SYMATTR InstName X10 SYMBOL INVy 1152 128 R0 SYMATTR InstName X11 SYMBOL INVy 1152 0 R0 SYMATTR InstName X12 SYMBOL 4Bit_DAC_pipe 1600 0 R0 SYMATTR InstName X8 SYMBOL 4Bit_DAC_pipe 1600 272 R0 SYMATTR InstName X9 SYMBOL cap 1792 272 R0 SYMATTR InstName C3 SYMATTR Value 2n SYMBOL res 1792 256 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1k SYMBOL Opamp3 -224 64 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X13 SYMATTR SpiceLine Aol=100000 GBW=0.1G SYMBOL res 352 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL res 320 144 R0 SYMATTR InstName R9 SYMATTR Value 1k SYMBOL Comp3 144 128 R0 SYMATTR InstName X3 SYMATTR SpiceLine Aol=1000000 GBW=1G TEXT 1120 -168 Left 2 !;.dc V3 -4.5 4.5 0.02 TEXT 1104 -136 Left 2 !.global VDDp VDDn VDD TEXT 432 -288 Left 2 !V1 VDDp 0 3\nV2 VDDn 0 -3\nV6 VREF 0 DC 0\nV3 INX 0 PULSE(-1.5 1.8 0 983.4m 983.4m 0 1966.8m)\nV4 VDD 0 2\nV5 IN 0 SINE(0.181 1.521 19.32779948) TEXT -152 368 Left 2 !.model CD4007N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model CD4007P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n) TEXT -160 -288 Left 2 !;VCLK1 CLK1 0 DC 3\n;VCLK2 CLK2 0 DC 3\n;VCLK3 CLK3 0 DC -3\nVCLK1 CLK1 0 PULSE(-3 3 5u 100n 100n 19.9u 480u)\nVCLK2 CLK2 0 PULSE(-3 3 30u 100n 100n 19.9u 60u)\nVCLK3 CLK3 0 PULSE(-3 3 55u 100n 100n 19.9u 60u) TEXT 1144 400 Left 2 !;.tran 0 983.4m 0 TEXT 1152 432 Left 2 !.save V(Vouty) TEXT 1120 -232 Left 2 !.options plotwinsize=0\n;.option numdgt=12 TEXT -96 96 Left 2 ;ay TEXT -176 -48 Left 2 ;by TEXT 648 208 Left 2 ;cy TEXT 64 192 Left 2 ;Op4 TEXT -312 152 Left 2 ;Op3 TEXT 432 256 Left 2 ;Op2 TEXT 840 296 Left 2 ;Op1 TEXT 592 272 Left 2 ;OP TL974 TEXT -136 160 Left 2 ;Switch\nCD4053 TEXT 1200 248 Left 2 ;serial\nparallel\nSN74HC595 TEXT 1152 360 Left 2 !.tran 0 983.4m 0
- Simulate a ramp signal with static CLKs and discuss the transfer characteristic.
Comment out the .save command to see all signals.
Deactivate the CLK PULSE statements and activate the static CLK DC statements.
Ramp or sine signal is selected by switching the node name form INX to IN in the respective statements.
Removing and inserting semicolons ; activates one or the other option.
Generating a positiv digital signal Dout from 0V to 3V requires R3 and R4 connected to VDDp.
On the left are the 2 switches selecting input voltage V(in) (CLK1) or V(res) (CLK3) from a pipeline stage operation.
The voltage Vin is saved as Vinx on sample and hold capacitor C1.
The comparator X3 generates data output Dout.
Vout = 2 * Vinx - Dout is generated by X1 and saved via a switch on C2 (CLK2) as Voutx. Buffer X6 feeds VoutX as residue Vres back to the input for the next cycle.
CLK 1 is shortly activated to sample V(in) and generate the first Dout. For the number of required bits CLK2 and then CLK 3 is activated generating the remaining bits.
V3 INX 0 PULSE(-1.5 1.8 0 983.4m 983.4m 0 1966.8m) V5 IN 0 SINE(0.181 1.521 19.32779948)This simulation contains static CLK for simulating transfer characteristic.
VCLK1 CLK1 0 PULSE(-3 3 5u 100n 100n 19.9u 480u) VCLK2 CLK2 0 PULSE(-3 3 30u 100n 100n 19.9u 60u) VCLK3 CLK3 0 PULSE(-3 3 55u 100n 100n 19.9u 60u) ;VCLK1 CLK1 0 DC 3 ;VCLK2 CLK2 0 DC 3 ;VCLK3 CLK3 0 DC 0Dynamic CLK statements (PULSE) are used for normal operation generating serially 8 bit at Dout.
Removing and inserting semicolons ; activates one or the other option.
Generating a positiv digital signal Dout from 0V to 3V requires R3 and R4 connected to VDDp.
On the left are the 2 switches selecting input voltage V(in) (CLK1) or V(res) (CLK3) from a pipeline stage operation.
The voltage Vin is saved as Vinx on sample and hold capacitor C1.
The comparator X3 generates data output Dout.
Vout = 2 * Vinx - Dout is generated by X1 and saved via a switch on C2 (CLK2) as Voutx. Buffer X6 feeds VoutX as residue Vres back to the input for the next cycle.
CLK 1 is shortly activated to sample V(in) and generate the first Dout. For the number of required bits CLK2 and then CLK 3 is activated generating the remaining bits.
Dynamic ramp simulation
- Simulate a ramp signal with CLK operation and calculate INL and DNL.
Save the LTSPICE raw file under C:\temp\raw.
Activate the .save command.
Activate the CLK PULSE statements and deactivate the static CLK DC statements.
What is the sample frequency?
What is the input range?
What is the output range of Vouty?
Extract data with Read Raw File. - Use the ramp signal for calibration
- How do CLK1, CLK2 and CLK3 control operation?
How many bits are generated? - How many samples are simulated?
- What is the resolution of INL, DNL calculation with this number of samples?
- What is the Vmax and LSB of the DAC?
- Optimize the simulation and extract INL and DNL
Dynamic sine simulation
- Simulate a sine signal with CLK operation and calculate INL and DNL.
Activate the .save command.
Activate the CLK PULSE statements and deactivate the static CLK DC statements.
Adjust the range of the sine signal to generate all codes?
What is the input range?
What is the output range of Vouty?
Extract data with Read Raw File . - Use the ramp signal for calibration
- Simulate a sine signal and calculate SNR, ENOB
- What are the optimum values for extraction and calculation?
- Simulate a sine signal and calculate SNR, ENOB with calibration
- How many samples are simulated?
- Is there a difference in INL and DNL between ramp and sine measurement?
What improvements could you apply to the circuit?
Building the circuit
- Opamps in the schematic are realized with TL974
- Sample and hold with switches are realized with CD4053
- Serial parallel conversion is done using a SN74HC595
- Since many connections are needed a step by step approach will be used.
- Opamp buffer characterization
- Sample and hold switch characterization
- Comparator measurement
- Residue generation
- Second sample and hold
- Closing the loop
- Shift register
DIO18: CLK1 A; fsample, up time: 1/50 Tsample, delay: 0
DIO17: CLK2 C; 8*fsample, up time: 1/4 Tsample, phase: 234°
DIO16: CLK3 B; 8*fsample, up time: 1/4 Tsample, phase: 90°
tswitch active = 1µs; works with relaxed Tswitch = 10 µs
fswitch1 = 12.5 kHz; Duty 2%; Phase 0 deg;
fswitch2 = 100 kHz; Duty 25%; Phase 234 deg;
fswitch3 = 100 kHz; Duty 25%; Phase 90 deg;
Input buffer Opamp
Opamp3.asc Opamp3.asy SwitchX.asc SwitchX.asy Shift8.asc Shift8.asy INVy.asc INVy.asy 4Bit_DAC_pipe.asc 4Bit_DAC_pipe.asy Shift.asc Shift.asy XSH.asc XSH.asy
Version 4 SHEET 1 2224 828 WIRE -224 32 -224 0 WIRE -256 48 -320 48 WIRE -160 64 -192 64 WIRE -112 64 -160 64 WIRE -256 80 -288 80 WIRE -288 112 -288 80 WIRE -160 112 -160 64 WIRE -160 112 -288 112 WIRE -224 128 -224 96 FLAG -320 48 In IOPIN -320 48 In FLAG -224 0 VDDp FLAG -224 128 VDDn FLAG -112 64 Vin1 SYMBOL Opamp3 -224 64 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X13 SYMATTR SpiceLine Aol=100000 GBW=0.01G TEXT 1120 -168 Left 2 !;.dc V3 -4.5 4.5 0.02 TEXT 1104 -136 Left 2 !.global VDDp VDDn VDD TEXT 440 -304 Left 2 !V1 VDDp 0 3\nV2 VDDn 0 -3\nV6 VREF 0 DC 0\nV3 IN 0 PULSE(-1.7 1.7 0 983.4m 983.4m 0 1966.8m)\nV4 VDD 0 2\nV5 INX 0 SINE(1 1 19.32779948) TEXT -136 416 Left 2 !.model CD4007N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model CD4007P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n) TEXT -192 -296 Left 2 !VCLK1 CLK1 0 PULSE(-3 3 5u 100n 100n 19.9u 480u)\nVCLK2 CLK2 0 PULSE(-3 3 30u 100n 100n 19.9u 60u)\nVCLK3 CLK3 0 PULSE(-3 3 55u 100n 100n 19.9u 60u)\n;VCLK1 CLK1 0 DC 3\n;VCLK2 CLK2 0 DC 3\n;VCLK3 CLK3 0 DC 0 TEXT 128 -176 Left 2 !;.tran 0 983.4m 0 TEXT 128 -144 Left 2 !;.save V(Vouty) TEXT 1120 -232 Left 2 !.options plotwinsize=0\n;.option numdgt=12 TEXT -312 152 Left 2 ;Op3 TEXT 136 -208 Left 2 !.tran 983.4mMeasure with the oscilloscope minimum and maximum output voltage, gain, bandwidth and slew rate limit.
Distribute VCC, VP-, VP+ and GND along the orange and blue lines on the bread board.
Apply VP+ = 3 V, VP- = -3V, VCC = 3.3 V via the 'Voltage' control panel.
Apply a sine or rectangular waveform to the input using the 'WaveGen' control panel.
Maximum input level:
Minimum input level:
Maximum slew rate:
Maximum bandwidth:
Is the maximum frequency limited by slew rate or bandwidth?
Connections:
Apply: VP+ 3V, VP- 3V, AWG1 sine, 0V offset, xx V amplitude
This is the last step for WS2019 to be completed.
Make a report as a web page.
Send a ziped group directory with your data containing also a printout of the webpage in a pdf file to joerg.vollrath@hs-kempten.de.
You can use the freeware program PDF Creator for generating the pdf file.
The directory should be named 2019_Group<X>00 with your group <X>.
Each question should be answered. The answer should be correct/make sense. There should be some text discussing the work strategy, obstacles and results. Submission should happen until 2.2.2020. A nice document format and correct use of English language and spelling is graded.
Apply VP+ = 3 V, VP- = -3V, VCC = 3.3 V via the 'Voltage' control panel.
Apply a sine or rectangular waveform to the input using the 'WaveGen' control panel.
Maximum input level:
Minimum input level:
Maximum slew rate:
Maximum bandwidth:
Is the maximum frequency limited by slew rate or bandwidth?
Connections:
| Net name | IC | pinNr | IC | pinNr |
| VP+ | TL974 | 4 | EE | VP+ |
| VP- | TL974 | 11 | EE | VP- |
| vin | TL974 IN3+ | 10 | EE | AWG1 |
| vin | EE | OSC1 | EE | AWG1 |
| vin1 | TL974 IN3- | 9 | TL974 OUT3 | 8 |
| vin1 | TL974 OUT3 | 8 | EE | OSC2 |
Apply: VP+ 3V, VP- 3V, AWG1 sine, 0V offset, xx V amplitude
Laboratory finish
This is the last step for WS2019 to be completed.
Report
Make a report as a web page.
Send a ziped group directory with your data containing also a printout of the webpage in a pdf file to joerg.vollrath@hs-kempten.de.
You can use the freeware program PDF Creator for generating the pdf file.
The directory should be named 2019_Group<X>00 with your group <X>.
Grading:
Each question should be answered. The answer should be correct/make sense. There should be some text discussing the work strategy, obstacles and results. Submission should happen until 2.2.2020. A nice document format and correct use of English language and spelling is graded.
Sample and hold
Opamp3.asc Opamp3.asy SwitchX.asc SwitchX.asy Shift8.asc Shift8.asy INVy.asc INVy.asy 4Bit_DAC_pipe.asc 4Bit_DAC_pipe.asy Shift.asc Shift.asy XSH.asc XSH.asy
Version 4 SHEET 1 2224 828 WIRE -80 0 -144 0 WIRE -80 16 -80 0 WIRE -224 32 -224 0 WIRE -256 48 -320 48 WIRE -160 64 -192 64 WIRE -112 64 -160 64 WIRE -16 64 -48 64 WIRE 48 64 -16 64 WIRE -256 80 -288 80 WIRE -288 112 -288 80 WIRE -160 112 -160 64 WIRE -160 112 -288 112 WIRE -224 128 -224 96 WIRE -16 144 -16 128 FLAG -320 48 In IOPIN -320 48 In FLAG -16 144 0 FLAG -144 0 CLK1 FLAG -224 0 VDDp FLAG -224 128 VDDn FLAG -160 64 vin1 FLAG 48 64 Vinx SYMBOL cap -32 64 R0 SYMATTR InstName C1 SYMATTR Value 20n SYMBOL SwitchX -80 64 R0 SYMATTR InstName X2 SYMBOL Opamp3 -224 64 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X13 SYMATTR SpiceLine Aol=100000 GBW=0.01G TEXT 1120 -168 Left 2 !;.dc V3 -4.5 4.5 0.02 TEXT 1104 -136 Left 2 !.global VDDp VDDn VDD TEXT 440 -304 Left 2 !V1 VDDp 0 3\nV2 VDDn 0 -3\nV6 VREF 0 DC 0\nV3 IN 0 PULSE(-1.7 1.7 0 983.4m 983.4m 0 1966.8m)\nV4 VDD 0 2\nV5 INX 0 SINE(1 1 19.32779948) TEXT -136 416 Left 2 !.model CD4007N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model CD4007P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n) TEXT -192 -296 Left 2 !VCLK1 CLK1 0 PULSE(-3 3 5u 100n 100n 19.9u 480u)\nVCLK2 CLK2 0 PULSE(-3 3 30u 100n 100n 19.9u 60u)\nVCLK3 CLK3 0 PULSE(-3 3 55u 100n 100n 19.9u 60u)\n;VCLK1 CLK1 0 DC 3\n;VCLK2 CLK2 0 DC 3\n;VCLK3 CLK3 0 DC 0 TEXT 128 -176 Left 2 !;.tran 0 983.4m 0 TEXT 128 -144 Left 2 !;.save V(Vouty) TEXT 1120 -232 Left 2 !.options plotwinsize=0\n;.option numdgt=12 TEXT -96 96 Left 2 ;ay TEXT -312 152 Left 2 ;Op3 TEXT -136 160 Left 2 ;Switch\nCD4053 TEXT 136 -208 Left 2 !.tran 983.4mMeasure with the oscilloscope limits of the sample and hold.
What sine frequency and amplitude do you need?
What clock frequency do you need for CLK1 for the switch?
Distribute VCC, VP-, VP+ and GND along the orange and blue lines on the bread board.
Added Connections:
Apply: VP+ 3V, VP- 3V, AWG1 sine, 0V offset, xx V amplitude
Generate a clock with DIO18
Added Connections:
| Net name | IC | pinNr | IC | pinNr |
| VSS | CD4053 VSS | 8 | EE | GND |
| VCC | CD4053 VDD | 16 | EE | VCC |
| vin1 | CD4053 ay | 16 | TL974 | 8 |
| CLK1 | CD4053 Sel A | 11 | EE | DIO18 |
| vinx | CD4053 OUT a | 14 | EE | OSC3 |
| GND | CD4053 INH | 6 | EE | GND |
| VP- | CD4053 VEE | 7 | EE | VP- |
| VINX | C1 | 1 | CD4053 OUT a | 14 |
| GND | C1 | 2 | EE | GND |
Apply: VP+ 3V, VP- 3V, AWG1 sine, 0V offset, xx V amplitude
Generate a clock with DIO18
Comparator
Opamp3.asc Opamp3.asy SwitchX.asc SwitchX.asy Shift8.asc Shift8.asy INVy.asc INVy.asy 4Bit_DAC_pipe.asc 4Bit_DAC_pipe.asy Shift.asc Shift.asy XSH.asc XSH.asy
Version 4 SHEET 1 2224 828 WIRE -80 0 -144 0 WIRE -80 16 -80 0 WIRE 368 16 336 16 WIRE 448 16 448 -16 WIRE 576 16 528 16 WIRE -224 32 -224 0 WIRE -256 48 -320 48 WIRE -160 64 -192 64 WIRE -144 64 -160 64 WIRE -112 64 -144 64 WIRE -16 64 -48 64 WIRE 48 64 -16 64 WIRE 96 64 48 64 WIRE 464 64 96 64 WIRE -256 80 -288 80 WIRE 144 96 144 32 WIRE -288 112 -288 80 WIRE -160 112 -160 64 WIRE -160 112 -288 112 WIRE 96 112 96 64 WIRE 112 112 96 112 WIRE -224 128 -224 96 WIRE 208 128 176 128 WIRE 224 128 208 128 WIRE 256 128 224 128 WIRE 336 128 336 16 WIRE 368 128 336 128 WIRE -16 144 -16 128 WIRE 112 144 80 144 WIRE 336 160 336 128 WIRE 512 160 512 112 WIRE 464 176 464 64 WIRE 480 176 464 176 WIRE 576 192 576 16 WIRE 576 192 544 192 WIRE 608 192 608 80 WIRE 608 192 576 192 WIRE 448 208 448 16 WIRE 480 208 448 208 WIRE 144 240 144 160 WIRE 144 240 48 240 WIRE 336 256 336 240 WIRE 128 304 112 304 WIRE 208 304 208 208 WIRE 240 304 208 304 WIRE 512 304 512 224 WIRE 512 304 432 304 FLAG 144 32 VDDp FLAG 48 240 VDDn FLAG -320 48 In IOPIN -320 48 In FLAG 608 80 Vout IOPIN 608 80 Out FLAG 432 304 VDDn FLAG 512 112 VDDp FLAG 240 304 Dout IOPIN 240 304 Out FLAG 80 144 Vref FLAG -16 144 0 FLAG -144 0 CLK1 FLAG 48 64 Vinx FLAG -224 0 VDDp FLAG -224 128 VDDn FLAG 112 304 VDDp FLAG 336 256 0 FLAG 224 128 Dx FLAG 368 128 Dy FLAG -144 64 vin1 SYMBOL res 544 0 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL Opamp3 512 192 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X1 SYMATTR SpiceLine Aol=100000 GBW=0.01G SYMBOL cap -32 64 R0 SYMATTR InstName C1 SYMATTR Value 20n SYMBOL res 192 112 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res 224 288 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL SwitchX -80 64 R0 SYMATTR InstName X2 SYMBOL res 464 0 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 33 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 120k SYMBOL Opamp3 -224 64 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X13 SYMATTR SpiceLine Aol=100000 GBW=0.01G SYMBOL res 352 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL res 320 144 R0 SYMATTR InstName R9 SYMATTR Value 1k SYMBOL Opamp3 144 128 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X3 SYMATTR SpiceLine Aol=100000 GBW=0.01G TEXT 1120 -168 Left 2 !;.dc V3 -4.5 4.5 0.02 TEXT 1104 -136 Left 2 !.global VDDp VDDn VDD TEXT 440 -304 Left 2 !V1 VDDp 0 3\nV2 VDDn 0 -3\nV6 VREF 0 DC 0\nV3 IN 0 PULSE(-1.7 1.7 0 983.4m 983.4m 0 1966.8m)\nV4 VDD 0 2\nV5 INX 0 SINE(1 1 19.32779948) TEXT -136 416 Left 2 !.model CD4007N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model CD4007P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n) TEXT -192 -296 Left 2 !VCLK1 CLK1 0 PULSE(-3 3 5u 100n 100n 19.9u 480u)\nVCLK2 CLK2 0 PULSE(-3 3 30u 100n 100n 19.9u 60u)\nVCLK3 CLK3 0 PULSE(-3 3 55u 100n 100n 19.9u 60u)\n;VCLK1 CLK1 0 DC 3\n;VCLK2 CLK2 0 DC 3\n;VCLK3 CLK3 0 DC 0 TEXT 128 -176 Left 2 !;.tran 0 983.4m 0 TEXT 128 -144 Left 2 !;.save V(Vouty) TEXT 1120 -232 Left 2 !.options plotwinsize=0\n;.option numdgt=12 TEXT -96 96 Left 2 ;ay TEXT 64 192 Left 2 ;Op4 TEXT -312 152 Left 2 ;Op3 TEXT 432 256 Left 2 ;Op2 TEXT 592 272 Left 2 ;OP TL974 TEXT -136 160 Left 2 ;Switch\nCD4053 TEXT 136 -208 Left 2 !.tran 983.4m
Document the transfer characteristic.
Added Connections:
Added Connections:
| Net name | IC | pinNr | IC | pinNr |
| Vinx | TLC974 IN4+ | 12 | Cd4053 OUTA | 14 |
| Vref1 | TLC974 IN4- | 13 | EE | Vref1(GND) |
| Dx | TLC974 OUT4 | 14 | R3 | 1 |
| Dout | R3 | 2 | R4 | 1 |
| VDDp | R4 | 2 | EE | VP+ |
| Dx | TLC974 OUT4 | 14 | R8 | 1 |
| Dy | R8 | 2 | R6 | 1 |
| Dy | R8 | 2 | R9 | 1 |
| GND | R9 | 2 | EE | GND |
| R6 | 2 | R5 | 1 | |
| R6 | 2 | TLC974 IN2- | 6 | |
| Vout | R5 | 2 | TLC974 OUT2 | 7 |
| Vinx | CD4053 OUTA | 14 | TLC974 IN2+ | 5 |
Residue
Opamp3.asc Opamp3.asy SwitchX.asc SwitchX.asy Shift8.asc Shift8.asy INVy.asc INVy.asy 4Bit_DAC_pipe.asc 4Bit_DAC_pipe.asy Shift.asc Shift.asy XSH.asc XSH.asy
Version 4 SHEET 1 2224 828 WIRE -80 0 -144 0 WIRE -80 16 -80 0 WIRE 368 16 336 16 WIRE 448 16 448 -16 WIRE 576 16 528 16 WIRE -224 32 -224 0 WIRE -256 48 -320 48 WIRE -160 64 -192 64 WIRE -144 64 -160 64 WIRE -112 64 -144 64 WIRE -16 64 -48 64 WIRE 48 64 -16 64 WIRE 96 64 48 64 WIRE 464 64 96 64 WIRE -256 80 -288 80 WIRE 144 96 144 32 WIRE -288 112 -288 80 WIRE -160 112 -160 64 WIRE -160 112 -288 112 WIRE 96 112 96 64 WIRE 112 112 96 112 WIRE -224 128 -224 96 WIRE 208 128 176 128 WIRE 224 128 208 128 WIRE 256 128 224 128 WIRE 336 128 336 16 WIRE 368 128 336 128 WIRE 736 128 672 128 WIRE -16 144 -16 128 WIRE 112 144 80 144 WIRE 736 144 736 128 WIRE 336 160 336 128 WIRE 512 160 512 112 WIRE 464 176 464 64 WIRE 480 176 464 176 WIRE 912 176 912 144 WIRE 576 192 576 16 WIRE 576 192 544 192 WIRE 608 192 608 80 WIRE 608 192 576 192 WIRE 704 192 608 192 WIRE 800 192 768 192 WIRE 816 192 800 192 WIRE 880 192 816 192 WIRE 448 208 448 16 WIRE 480 208 448 208 WIRE 976 208 944 208 WIRE 880 224 848 224 WIRE 144 240 144 160 WIRE 144 240 48 240 WIRE 336 256 336 240 WIRE 848 256 848 224 WIRE 976 256 976 208 WIRE 976 256 848 256 WIRE 800 272 800 256 WIRE 912 272 912 240 WIRE 128 304 112 304 WIRE 208 304 208 208 WIRE 240 304 208 304 WIRE 512 304 512 224 WIRE 512 304 432 304 FLAG 144 32 VDDp FLAG 48 240 VDDn FLAG -320 48 In IOPIN -320 48 In FLAG 608 80 Vout IOPIN 608 80 Out FLAG 432 304 VDDn FLAG 512 112 VDDp FLAG 240 304 Dout IOPIN 240 304 Out FLAG 80 144 Vref FLAG -16 144 0 FLAG 800 272 0 FLAG 912 144 VDDp FLAG 912 272 VDDn FLAG -144 0 CLK1 FLAG 672 128 CLK2 FLAG 48 64 Vinx FLAG 816 192 Voutx FLAG -224 0 VDDp FLAG -224 128 VDDn FLAG 112 304 VDDp FLAG 336 256 0 FLAG 224 128 Dx FLAG 368 128 Dy FLAG -144 64 vin1 SYMBOL res 544 0 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL Opamp3 512 192 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X1 SYMATTR SpiceLine Aol=100000 GBW=0.01G SYMBOL cap -32 64 R0 SYMATTR InstName C1 SYMATTR Value 20n SYMBOL cap 784 192 R0 SYMATTR InstName C2 SYMATTR Value 20n SYMBOL Opamp3 912 208 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X6 SYMATTR SpiceLine Aol=100000 GBW=0.01G SYMBOL res 192 112 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res 224 288 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL SwitchX -80 64 R0 SYMATTR InstName X2 SYMBOL SwitchX 736 192 R0 SYMATTR InstName X5 SYMBOL res 464 0 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 33 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 120k SYMBOL Opamp3 -224 64 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X13 SYMATTR SpiceLine Aol=100000 GBW=0.01G SYMBOL res 352 112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL res 320 144 R0 SYMATTR InstName R9 SYMATTR Value 1k SYMBOL Opamp3 144 128 R0 WINDOW 0 33 -18 Bottom 2 SYMATTR InstName X3 SYMATTR SpiceLine Aol=100000 GBW=0.01G TEXT 1120 -168 Left 2 !;.dc V3 -4.5 4.5 0.02 TEXT 1104 -136 Left 2 !.global VDDp VDDn VDD TEXT 440 -304 Left 2 !V1 VDDp 0 3\nV2 VDDn 0 -3\nV6 VREF 0 DC 0\nV3 IN 0 PULSE(-1.7 1.7 0 983.4m 983.4m 0 1966.8m)\nV4 VDD 0 2\nV5 INX 0 SINE(1 1 19.32779948) TEXT -136 416 Left 2 !.model CD4007N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model CD4007P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)\n.model P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n) TEXT -192 -296 Left 2 !VCLK1 CLK1 0 PULSE(-3 3 5u 100n 100n 19.9u 480u)\nVCLK2 CLK2 0 PULSE(-3 3 30u 100n 100n 19.9u 60u)\nVCLK3 CLK3 0 PULSE(-3 3 55u 100n 100n 19.9u 60u)\n;VCLK1 CLK1 0 DC 3\n;VCLK2 CLK2 0 DC 3\n;VCLK3 CLK3 0 DC 0 TEXT 128 -176 Left 2 !;.tran 0 983.4m 0 TEXT 128 -144 Left 2 !;.save V(Vouty) TEXT 1120 -232 Left 2 !.options plotwinsize=0\n;.option numdgt=12 TEXT -96 96 Left 2 ;ay TEXT 648 208 Left 2 ;cy TEXT 64 192 Left 2 ;Op4 TEXT -312 152 Left 2 ;Op3 TEXT 432 256 Left 2 ;Op2 TEXT 840 296 Left 2 ;Op1 TEXT 592 272 Left 2 ;OP TL974 TEXT -136 160 Left 2 ;Switch\nCD4053 TEXT 136 -208 Left 2 !.tran 983.4m
Added Connections:
| Net name | IC | pinNr | IC | pinNr |
| Vout | TLC974 OUT2 | 7 | CD4053 CY | 3 |
| CLK2 | CD4053 C | 9 | EE | DIO17 |
| Voutx | CD4053 OUTC | 4 | TLC974 IN1+ | 3 |
| Voutx | CD4053 OUTC | 4 | C2 | 1 |
| GND | C2 | 2 | EE | GND |
| Vres | TLC974 OUT1 | 1 | TLC974 IN1- | 2 |
Finish
Added Connections closing the loop:
| Net name | IC | pinNr | IC | pinNr |
| Vres | TLC974 OUT1 | 1 | CD4053 BY | 1 |
| CLK3 | CD4053 B | 10 | EE | DIO16 |
| Vinx | CD4053 OUTB | 15 | TLC974 IN4+ | 12 |
Serial parallel:
| Net name | IC | pinNr | IC | pinNr |
| Dout | R3 | 2 | SN74HC595 SER | 14 |
| D0 | SN74HC595 D0 | 15 | EE | DIO8 |
| D1 | SN74HC595 D1 | 1 | EE | DIO9 |
| D2 | SN74HC595 D2 | 2 | EE | DIO10 |
| D3 | SN74HC595 D3 | 3 | EE | DIO11 |
| D4 | SN74HC595 D4 | 4 | EE | DIO12 |
| D5 | SN74HC595 D5 | 5 | EE | DIO13 |
| D6 | SN74HC595 D6 | 6 | EE | DIO14 |
| D7 | SN74HC595 D7 | 7 | EE | DIO15 |
| GND | SN74HC595 GND | 8 | EE | GND |
| VCC | SN74HC595 /SRCLR | 10 | EE | VCC |
| C | SN74HC595 SRCK | 11 | EE | DIO17 |
| A | SN74HC595 RCK | 12 | EE | VCC |
| VCC | SN74HC595 VCC | 16 | EE | VCC |
| SN74HC595 /G | 13 |