Hochschule Kempten      
Fakult├Ąt Elektrotechnik      
Interface Electronics       Fachgebiet Elektronik, Prof. Vollrath      

Interface Electronics

Laboratory 01

GroupB1, ****38, H


installation of Webpage

Test for 4 Bit ADC and DAC

A 4 Bit ADC and DAC test can be simulated in LTSPICE.
the file were downloaded and LTSPICE simulation was started.
The output file size can be limited by using the .save dialog option.

A voltage source was added with a ramp from 0to 1V with a rise time of 655µs.
The picture shows a ramp input Voltage and the DAC ramp output voltage over 16 steps can be seen. with amesurments tatement the voltage levels were extracted
.Measure TRAN V0000 FIND V(Vout) AT= 20u

at 60ustimethe output of 0.0625 V is given for the code 0001.
V0001: V(out)=0.0625 at 6e-005

No error in the voltage level can be seen. it is an ideal ADC and DAC.

LTSPICE schematics

JavaScript module

From the results it is clear that it is a real DAC, since we could see transition inthe voltage (due to transistor's C and R), also the different in R is responsible of inducing errors.

Calculating DNL and INL:
The first step is to calculate LSB=3.5/7=0.5v
INL (011)= (Vreal-Videal)/LSB= -0.4v
DNL= (Vn-Vn-1-LSB)/LSB=0.2v


  • This Lab allowed us to get more into HTML and Webpage creation, furthermore it allowed us to simulate different types of DAC. In case of real DAC we were wble to see errors and calculating INL and DNL.


[1] Making of a Webreport , Vollrath