# Overview

• Low pass filter simulation with RC Circuit

• Determine -3dB frequency of filter

• Simulation of 4 bits ADC-DAC circuit

• Simulation Analysis

• Interpretation of Results

# Abstract

• First two weeks of the lecture ; low pass filter , designing principles , ADC-DAC integrated circuit and simulations were discussed.

• Based on the what we learned this webreport refers the LTSpice simulation of Low Pass Filter and ADC-DAC circuits which widely use in electronic devices for different purposes.

• Initially, Low Pass Filter and cut off frequency will be monitored. Afterwards 4-Bits Behavioural ADC-DAC circuit and simulational output will be evaluated.

• For ADC-DAC convertors; any deviation from ideal step width called as a Differential-Non Linearity (DNL) and maximum deviation from ideal line called as Integral-Non Linearity (INL).

Those inevitable errors shows us performance of conversion and can not remove with calibration.At the last section of report , 3-Bits DAC circuit will be simulated. Calculated DNL ,INL

values will be shown in table and output signal and ideal signal will be compared.

# Low Pass Filtering Circuit

Designed circuit for analysing output of sine wave with 1V amplitude between 10 Hz to 1 kHz frequency range. R=100k & C=50nF are connected series and energized with voltage source.

In this case for higher frequencies C1 behaves like open circuit and due to low inductance of C1 , high frequency signals accumulate voltage on R1.

C1 is the component which controls output of circuit so it reflects only lower frequency signals to output. Main purpose of this filter is attenuate higher frequency signals.

For drawing circuit and simulation LTSpice and " .op , .ac ,.tran , .dc " commands were commonly used for transient , DC , AC analyses of circuit.

# Simulation of Low Pass Filter in LTSPICE

Running LTSpice Simulation with transient (.tran) command visualize input and output signals in time domain with amplitudes.

Blue line show us 1 V AC vawe line with 3V of DC offset value and green line is DC output of circuit. Phase shift is also clearly visible due to affect of capasitor.

Since LTSpice is a simulation tool , we can simulate more wider range of time scale and place also values like IR , IC , IVin as well. After simulate Low Pass Filter circuit in time domain , basicly enable .ac command in decade mode with frequency between 10Hz and 1Khz.

Analysing signal in frequency domain shows -3dB cut-off frequency of signal and the angle of phase shift due to affect of capasitor. The frequencies behind this will be attenueted by filter due to less gain.

(1/2*pi*R*C) = 31.8 Hz. Hereby , we can confirm our calculation very closely in simulation graph. It can be seen in dash marked point below ; Magnetude= -3dB and Phase Shift= -44.93 degree

At higher frequencies Low Pass Filter suppress the signal amplitude and reduce the gain. 4 Bits ADC-DAC circuits can be shown below.Input signal enters from (in1) to ADC with feed voltage and clock pulse signal and can be visible as a digital output(D0, D1 , D2 , D3). Residual voltage will follow the way of output RES1.

Digital Outputs will became input of DAC to create analog signal and can be graphable on Vout with resolution of 2^4=16 steps. Above stated LTSpice circuit visualize the circuit with following commands. As seen also Low Pass Filter ; sine wave and clock pulse defined with frequency and start and stop transients of circuits are placed as well.

.save command is used for record memory and visualaze Vin , Vout signals.

# Simulation of 4 Bits DAC - ADC Circuit

Input V(in) and Output (Vout) signals are labelled below.As mentined above output of 4-Bits (2^4=16) steps are more appear.

If simulation done by 12 bits of ADC-DAC circuit resolution will be very high and output signal would approach to input signal more.

Indicated amplitudes and frequency steps at command section also clearly seen in graph.

Changing frequency of SINE line will create deviation and errors from Input signal.It can be seen basicly doubling frequency. In this graph , the period of clock pulse signal (CLK) which stated in command line ; changed from 10n to 10000n.Up to 15us (almost) first peak only 2 steps can visible though it was 8 at first graph.

Also this made deviation from Input signal wave. Not a good conversion for approach to analog signal at beginning. # DNL - INL Calculation of 3-Bits DAC Circuit

 Code V(out) V(ideal) DNL INL 0 0.0000 0 -0.200048 3.7601E-12 1 0.4000 0.5 -0.023526 -0.200048 2 0.8882 1 0.304154 -0.223574 3 1.54029 1.5 -0.01668 0.08058 4 2.03195 2 0.0224 0.0639 5 2.54315 2.5 -0.09504 0.0863 6 2.99563 3 0.00862 -0.00874 7 3.49994 3.5 -7.99988 -0.00012

Calculated DNL , INL values of 3-Bits DAC circuit on right side; showed on the table above with LSB= 0.5 . It is also clearly visible V(out) deviaton from V(ideal).

# Results

Exercise - Lab01

• As learned on first and second weeks , designing and implementation of Low Pass Filter and ADC-DAC exercises has explained in report.

• Drawings and simulation graphs are used for visualizing data of outputs.Tangible datas are obtained from LTSPICE Simulation tool.

• RC circuit Low Pass Filter (R=100k , C=50nF) and cut-off frequencies has shown and confirmed in LTSPICE Graph. Its also visible , out of the frequency range filter makes gain loss at output signal.

• Also drawing, outputs, inputs and commands of LTSPICE ADC-DAC circuit has learned and explained above. The affects of changing input signal frequency and deviations has surveyed.

• Effectively application of LTSPICE Software and commands are repeated.

• 3-Bits DAC circuit simulated on LTSPICE and voltage steps measured with command of ".MEAS TRAN".

• Using LSB value ; DNL , INL errors calculated and illustrated in table

• The correlation which shows DNL and INL deviations between V(out) & V(ideal) can be seen in graph.

• # References

 Making of a Webreport , Vollrath