Interface Electronics

Laboratory 03 - Web Report

GroupC04, ****61, O

Overview

Simulation analyses of RAMP signal with LTSPICE

Extracting of INL , DNL graphs with different step sizes and interpretation

Simulation analyses of SINE signal with LTSPICE

Extracting of ADC- DAC INL , DNL Histogram Graphs

FFT analyses of sine signal and interpretation of SNR

Simulation Analyses of ideal 4- Bits R2R ADC-DAC

Simulation , FFT , SNR analyses of edited 4- Bits R2R ADC-DAC circuit with SINE and RAMP waves

Interpretation of Results

Simulation Analyses of 4-bit ADC DAC with Ramp and Sine Wave

* Ramp Wave LTSPICE Drawings and INL , DNL Analyses with JavaScript Simulation

The graphs show simulation of setted ideal ADC-DAC circuit with ramp signal ( V1 in1 0 PULSE() ) in 655.36 micro seconds of transient time.

Output of ramp wave can be visible in graph.As it is 4 bits 16 signal steps are clearly showed in graph. Vertical spikes show output voltage of DAC and horizontal ones are LSBs of ADC output.

4Bit_ADC_DAC_pipe.asc

code4Bit_ADC_DAC_pipe

Due to 16 codes output , we analyse signal with 40.96u step size to see INL and DNL errors.But since this is an ideal wave there is no deviation from ideal signal it means DNL=0 , INL=0.

We can look more in to each steps with changing step size on JavaScript simulation.At 5.12 microseconds we are able to see 8 points each steps.

There are some deviations from ideal signal due to increasing time step but since its ideal histogram test stepsizes are all same for every code.

Because of increased code small shift can be visible in graph but it will not affect total INL value.

Differences between the signal and green line especially at beginning and end codes due to increased code each step DNL , INL can be seen in graph output of DAC.

But output of ADC shows that our signal is still ideal so DNL ,INL is 0.

* Sin Wave LTSPICE Drawings and INL , DNL and FFT Analyses with JavaScript Simulation

Initially via enabling voltage source in LTSPICE V2 in1 0 SINE , we can get our output graph as it shown down.

To get more understandable data we will use JavaScript simulation to see steps with filtered stepsize.

16 steps of signal in sine graph and their reflection in data integer points graph shows that our signal is nearly ideal.

Time data integer can confirm highest code voltage within transition time.

16 codes and DNL , INL distrubition is graphed below..

INLmax: 0.5 INLmin: -0.67 DNLmax: 19 DNLmin: -0.5 Missing Codes: 0
Minimum: 0 Maximum: 15 Delta: 15 Average: 7.5

FFT of sine signal shows us the frequency distribution of codes. We can see our strongest one at 16KHz , frequency #11 with magnetude of 11.87dB

JavaScript simulation gives us more filtered version of FFT compare to LTSPICE. We can see embedded white noises also in this graph but easy to determine SNR.

Signal to Noise ratio shows us the rate of unwanted noise inside our signal.And also ENOB can be calculated from here so we can see that we have no loss of bits due to signal and noise magnitude at frequency #11.

Frequency	Signal Magnitude dB	Total Noise Magnitude
11	11.87	-13.89
5	-21.56	-14.7
17	-23.64	-15.3
55	-24.16	-15.9
61	-25	-16.47
51	-25.62	-17.04
33	-25.67	-17.68
63	-26.33	-18.31
3	-26.86	-18.96
57	-27.66	-19.59
1	-28.4	-20.21

Simulation Analyses of 4-Bits R2R DAC with Ramp and Sine Wave

* LTSpice Analyses

R2R is the simplest way that we can design DAC with couple of R and C.Initially we will start with ideal R2R circuit after , we will edit some resistors on digital inputs to analyse changed output wave and INL , DNL errors that we created.

Easly we can draw circuit with LTSPICE with defining R2R DAC as a output.

4Bit_ADC_DAC_pipe_lab_3.asc

code4Bit_ADC_DAC_pipe_lab_3

As it can be see basicly on circuit diagrams our ideal circuit and output wave(left) sits excatly on input ramp signal.And stepsizes and output voltage of every code looks balanced.

To analyse DNL - INL errors as we change the R9(1.4k) and R6(1.7k) , we can see the the differences on vertical spikes which shows output voltage of DAC.

Do same analyses with simply switching voltage source to SINE vawe then as we can see graphs above , changed resistor value at last bit affected almost 0.25V jump also 3rd bit 0.1V jump as well.

* Ramp Signal ADC-DAC DNL, INL Analyses via JavaScript Simulation

With uploading our LTSPICE.raw file to JavaScript Simulation , the INL,DNL errors can be visible at below.

As we can see DAC Extracted Time Data graph the resistor caused difference from ideal line.Almost at the middle the deviation is maximum.If we see point by point , our DNL as stated on right side.

At the middle we have a big spike caused by resistor change at highest bit.Also two spike also appeared.Green line shows total DNL so INL error of our ramp signal.

The graphs above shows ADC Histogram test results of ramp signal.DNL , INL reflection from time data integer graph which shows distrubition of codes at ADC output can be seen.

* Sine Signal ADC-DAC Histogram Test - DNL, INL ,FFT and SNR Analyses via JavaScript Simulation

The graph stated below shows INL , DNL distribution of R2R DAC circuit with edited R9 and R6 resistance values.

As we can see the Histogram of 16 codes , DNL and INL errors vary quite much so it will give us a loss from bits in FFT.

INLmax: 2 INLmin: -1.5 DNLmax: 19 DNLmin: -1 Missing Codes: 4
Minimum: 0 Maximum: 15 Delta: 15 Average: 7.5

FFT analyses of R2R DAC Circuit is graphed above via JavaScript Simulation.Even though more noises JavaScript Simulation graph still more clear than LTSPICE FFT.

The stated SNR table shows the changes of magnitudes due to edited resistors in circuit.

Frequency #11 still our strongest one but magnitude is not same as before.Signal and Total Noise Magnitudes shows ENOB=3 so it means due to higher errors we lost a bit.

Frequency	Signal Magnitude dB	Total Noise Magnitude
11	12.23	-6.02
33	-9.33	-8.75
7	-13.15	-10.71
29	-18.44	-11.51
3	-19.86	-12.2
5	-19.96	-12.99
1	-21.58	-13.64
51	-22.87	-14.19
17	-22.99	-14.81
37	-23.1	-15.5
19	-23.22	-16.31

Interpretation of Results

We simulated ideal ramp signal with 40.96u step size and observed that steps and voltage outputs of each code are balanced. In that case we got no INL, DNL errors.

Repeat simulation with 5.12u step size so we can see more occurances each code.Due to increased resolution INL line started from left occurances and ended right on top
so we observed shift on our extracted time data so we got DNL , INL errors at DAC but it did not affected our ADC output we got 0 errors at INL and DNL.

Continiued simulation with sine signal and we checked amount of steps and amplitude of signal at LTSPICE output.With uploading our raw file to JavaScript Simulation we observed INL , DNL
and Histogram tests but there was no missing code.

With mapping integers we plotted FFT of sinus signal.In frequency domain we confirmed frequency of codes and highest magnitude it is at 16KHz even LTSPICE FFT it was clearly visible.

Calculated efective number of bits and since our signal is close to ideal we did not get loss of bit.Even FFT showed us white noises with frequencies in signal envelope.

Then we updated our circuit with R2R DAC output which is more easy and simple DAC we are going to use at Lab_4 exercise.Drew ideal R2R DAC circuit sine and ramp output graphs with LTSPICE

and observe ideal curve stepsizes and voltage outputs.Then to analyse DNL , INL errors , we edited ideal R2R circuit with change R9 to 1.4k and R6 to 1.7k after repeat LTSPICE simulation

As we can see also in graphs we got visible errors on output voltages around 0.25 and 0.1 volt amplitudes. Repeated this for sine and ramp wave by switching voltage source in directive line.

With JavaScript simulator ,Initially for ramp signal , we obtain the distrubition of DAC- ADC INL , DNL errors which we caused.A big spike and 2 small spike occured at our INL value output of DAC which is result of

changed resistances at 4th and 3rd bit inputs.Also ADC Histogram test showed us deviances at 16 codes.

Repeat histogram test analyses for sine vawe of R2R DAC circuit and graphed INL , DNL histogram.Due to errors we created , calculation of INL & DNL errors indicated 4 missing codes available it means 1 bit loss.

As a last step observed signal in frequecy domain with JavaScript FFT Simulation then the changes of SNR was appear in table compared to the previous sine signal FFT analyse.

FFT Graph shows strongest frequency in our signal and white noises around it within frequecy range of our signal.Also we confirmed by calculating loss of 1 bit with ENOB formula using signal and total noise magnitudes at Frequency #11.

Lab_3 exercise has completed.Results with graphs and comments are recorded.

2020 10 19 Interface Electronics Web report GroupC04 Ozdilek