Interface Electronics

Laboratory 01/02

GroupC7, ****97, S

Overview

Introduction
Zip files for basic setup
Launch LTSPICE
Simulation Commands:.op,.dc,.tran,.ac for RC circuit
Simulate hierarchical 4Bit_ADC_DAC_pipe in LTSPICE
Design Low pass filter with 3dB frequency
INL and DNL calculation of 3Bit_DAC
Challenges and Difficulties
Lessons learned and Timing
Summery
References

Introduction

Lab goal: To understand the operation of Data Converters and Low Pass Filter.

Basic Setup

Download web_Template.zip file from https://personalpages.hs-kempten.de/~vollratj/InEl/Vollrath_InEl.html
Unzip it and look into web_Template\InEl_P2019\2019_GroupX
Modify the name of folders and .html (InEl_P2020\2020_GroupC7_Susmita)

Launch LTSPICE

Open LTSPICE and construct random RC circuit.
Simulate some specific command to check circuit response.

Simulation Commands

.op = DC operation point.Check netlist and run the simulation for examining circuit values.
DC Swipe = Compute DC operating point while stepping independent sources and treating capacitance as open and inductance as short circuit.
Transient = Perform a non-linear, time-domain simulation.Apply sine wave in voltage source.
AC analysis = Compute small signal AC behavior linearized about it's DC operating point.
Measurement statement = .MEAS TAX WHEN V(vin)=2.4 FALL=4.To measure certain time when input voltage is 2.4 and look into 4th falling edge.

Test for 4 Bit ADC and DAC

A 4 Bit ADC and DAC test can be simulated and analyzed in LTSPICE.

The output file size can be limited by using the .save dialog option.

A analog input voltage source was added with ramp from 0V to 1V with a rise time of 655µs to do histogram test.

X4 presents ADC which digitalized 4 bits of data and X2 presents DAC with clock and 4 digital inputs and 1 voltage output.
The output shows the upper ramp step size of the digitalisation.

The picture shows a ramp input voltage and the DAC ramp output voltage over 16 steps can be seen.

With a measurement sataement the voltage level is like .Measure TRAN V0000 FIND V(Vout) AT=20u

No error in the voltage level can be seen.It is an ideal ADC and DAC.

Design Low Pass Filter

voltage source (sine,AC with amplitude of 1V)
R1 = 100k
C1 = 50 n
Spice directives =(.Op, .tran, .ac)

Transient simulation: red and blue lines represent input and output voltages respectively.

The amplitude of output voltage is lower due to resistor and due to capacitive effect it delays.

It can be assumed that frequency of 3dB is around 18.5 to 19.5 Hz which is corner frequency means it will filter signal over this value.

INL and DNL calculation of 3Bit_DAC

INL= Integral non linearity; DNL= Differential non linearity.

At 1.95us, output voltage 0.4V is given for the code V0001.

There is transistor switchs.So when input voltages change because of changing transection on/off of transistors,it generates a spike.

Doing the LSB, DNL and INL manual calculation using formulas.

Challenges and Difficulties

Editing html code according to web report because having no pre-knowledge about this language.
Access local files from files is not possible in chrome.

Lessons learned and timing

Familiar with LTSPICE and its different spice directives.
First experience about web report
Starting as a beginner learner of html language.
Using Notepad++ and Firefox for editing webpage html and access local files as chrome is not suitable for this.

Summery

After this lab,we can make a web report in html and observe some LTSPICE circuit simulation.

2020 10 25 Interface Electronics Web report GroupC7_Susmita