Overview

• Introduction
• 4-Bit ADC DAC setup
• Simulation and analysis of a ramp signal: DNL, INL, LSB
• Simulation and analysis of a sine signal: FFT, DNL, INL, SNR
• Simulation of R2R DAC
• Extract data with measurement statements
• Challenges and Difficulties
• Lessons learned and Timing
• Summery
• References

Introduction

• Lab goal:To test real ADC DAC with ideal ADC DAC by simulating ramp and sinusoidal signals with data converter analysis using LTspisce.

4-Bit ADC DAC setup

• Simulations with given ideal schematics were conducted.
• input voltage = sine signal; offset = 0.5; amplitude = 0.5; frequency = 16kHz.
• Clock supply : For every 10n there is a sample for ADC and DAC.
• Simulate transient (.tran 0 655.36u 0 1n) to get 655.36 samples.

• 11 periods; FFT Test in LTSpice.

• Input signal is better than output; hard to get all the values for harmonics, need to do external data process.

• Step size should be fixed to get ADC and DAC transfer characteristics to calculate INL and DNL and histogram test.

• Use javascript tool to do filtering the signal.

Simulation and analysis of a ramp signal: DNL, INL, LSB

• For DAC : Divide simulation time by 16 results 40.96us.

• Load the raw file into tool and get desired curves.

• For Exracted values.

• For Integer values.

• For DAC INL and DNL analysis.

• Ideal ADC histogram with smaller step size 5.12us.

Simulation and analysis of a sine signal: FFT, DNL, INL, SNR

• For DAC : With smaller step size 5.12us.

• Odd number cycles; each waveform covers all the codes.

• For Integer values.

• Ideal ADC histogram.

• Use FFT data processing tool; input integer data wher number of points =128 and number of bits =10.

• shows limited points, some values are missing, some gives noise of the signal.

• SNR 11.87-(-13.89) dB = 25.76 dB ENOB = (15.76-1.76)/6.02 = 4 Bits.

• Real INL and DNL .

• INL and DNL values obtained between +0.5 and -1.

Simulation of R2R DAC

• Include R2R DAC into ideal DAC ADC circuit using LTSPICE
• To fill in error, we modify R values: (R6) 1.3k, (R9) 1.5k.
• For sine signal:

• Load the file in javascript tool

• From FFT data processing tool:

• INL and DNL values obtained beyond +0.5 and -1 which can be concluded due to the non optimisation of the DAC parameters
• SNR 12.09-(-6.75) dB = 18.84 dB, lost 1 bit, 3 bits remain.
• For ramp signal:

• From read raw file tool:

• INL and DNL with error; big jumps on higher and lower order bits.

Extract data with measurement statements

• Insert SPICE directive:.meas trans OUT00 FIND V(vout) AT=81.92us.
• After simulation,"SPICE Error log" will show the result.
• Multiple measurement statements can be placed into a .meas script file.
• Data extraction can be difficult and quite time consuming.

Challenges and Difficulties

• Circuit files are not showing in the browser.That's why I used the circuit picture.

Lessons learned and timing

• Observed real and ideal ADC and DAC circuits behaviour with ramp and sine signals.
• Takes 6 hours to make the web report.

Summery

• After this lab,we know the data analysis process for real and ideal ADC and DAC circuits.