Hochschule Kempten      
Fakult├Ąt Elektrotechnik      
Interface Electronics       Fachgebiet Elektronik, Prof. Vollrath      

Interface Electronics

Laboratory 01

GroupD01, ***03, ARN

ADC and DAC LTSpice simulation



Overview

Installation of webpage

Test for 4 Bit ADC and DAC

A 4 Bit ADC and DAC test can be simulated in LTSPICE.
The files were downloaded and LTSpice simulation was started
The output file size can be limited by using the .save dialog option.

A voltage source was added with a ramp from 0 V to 1 V with a rise time of 655 µs.
The picture shows a ramp input voltage and the DAC ramp output Voltage over time.
16 steps can be seen. With a measurement statement the voltage levels were extracted.

.Measure TRAN V0000 FIND V(Vout) AT=20u

At 60 µs time the output of 0.0625 V is given for the code 0001.
V0001: V(Vout)=0.0625 at 6e-005

LTSPICE schematics

JavaScript module
SPICE_HTML_2018_02/LTSPICE.js

Canvas, Control, Link, Code parts

Add schematics to processing list

ID has to be the same as the schematic name.

INL and DNL error

Summary

Things learned

Problems solved

References


[1] Making of a Webreport , Vollrath