Overview

• Install Webpage Template
• Simulation Analysis
• Summary

Installation of Webpage

• Unzip the file
• Go to Directory InEl_P2019
• Copy Directory 2019_GroupX to 2020_GroupD03_Nwanji
• In the directory copy the file: 2017_Group01_V00.html to 2020_GroupD03_V1_Nwanji.html
• Edit with Notepad or other text editors 2020_GroupD03_V1_Nwanji
• Change the header, Change the footer, Edit Slides

Test for 4 Bit ADC and DAC

 A 4 Bit ADC and DAC test was simulated in LTSPICE. The 4bit ADC_DAC_Pipe.asc file was downloaded from reference page and ran with LTSpice The output file size was limited by using the .save dialog option on just the V(In1) and V(Vout). A voltage source was added and given a ramp from 0V to 1V with a rise time of 655µs The output shows the step size of the digitalisation after a ramp input signal was initialized. The picture shows a ramp input voltage and a DAC ramp output voltage over time 16steps can be seen. With a measurement statement (for the 16steps),e.g .Measure TRAN V0004 FIND V(Vout) AT=180u ,the voltage levels were extracted The measurement results are given below; V0000: V(Vout)=0 at 2e-005 V0001: V(Vout)=0.0625 at 6e-005 V0002: V(Vout)=0.125 at 0.0001 V0003: V(Vout)=0.1875 at 0.00014 V0004: V(Vout)=0.25 at 0.00018 V0005: V(Vout)=0.3125 at 0.00022 V0006: V(Vout)=0.375 at 0.00026 V0007: V(Vout)=0.4375 at 0.0003 V0008: V(Vout)=0.5 at 0.00034 V0009: V(Vout)=0.5625 at 0.00038 V0010: V(Vout)=0.625 at 0.00042 V0011: V(Vout)=0.6875 at 0.00046 V0012: V(Vout)=0.75 at 0.0005 V0013: V(Vout)=0.8125 at 0.00054 V0014: V(Vout)=0.875 at 0.00058 V0015: V(Vout)=0.9375 at 0.00062 Interpretation of Results Example; V0004: V(Vout)=0.25 at 0.00018 means At time 180µs, the output of 0.25V is given for the code 0004 No error in the voltage level can be seen. It is an Ideal ADC and DAC

3Bits DAC

A 3Bits DAC consisting of inverters was investigated and results collated
Voltages were outputted by operating the inverter switches with digital pulses from 0V to 5V in a regular pattern as seen in the spice command
The simulation was done and the transfer characteristics was captured; see pictorial graph

Errors in voltage levels can be seen
Errors exist because the input resistances in the circuit are irregular

The output voltage(real) at specific codes and times were collated as shown in table below
The ideal voltage was computed so that the time width between steps is one LSB (apart from the first code 000)
The DNL and INL were computed based on the formulae stated below and the results tabulated.
Step size:

$LSB = \frac{V(007) - V(000)}{2^{3}-1} = 0.5 V$

The step size between 2 successive codes is normalized with LSB and calculated as DNL:

$DNL(n) = \frac{ V(n) - V(n-1) - LSB}{LSB}$

The difference between real and ideal curve is normalized with LSB and calculated as INL:

$INL(n) = \frac{ V_{real}(n) - V_{ideal}(n)}{LSB}$

Tabulated results are shown below;

 Code 000 1 2 3 4 5 6 7 Time [µs] 0.95 1.95 2.95 3.95 4.95 5.95 6.95 7.95 Vout[V]ideal 0.00 0.5 1 1.5 2 2.5 3 3.5 Vout[V]real 0.00 0.4 0.9 1.55 2.04 2.55 3 3.5 DNL [LSB] -0.2 0 0.3 -0.02 0.02 -0.1 0 INL [LSB] 0.00 -0.2 -0.2 0.1 0.08 0.1 0 0

Challenges and Resolutions

Considering the fact that this is my first web report, time was consumed in putting up the report because I was discovering new things.
Initaiily, the schematics of my circuit was not displaying; I had to run about:config on Firefox and set set privacy.file_unique_origin to false, then all was good

Conclusion

Since the INL is calculated using the first and last code:
INL(000) = 0; INL(007) = 0;

DNL does not exist for the first code 000

References

[1] Making of a Webreport , Vollrath