Outline

• VHDL description of a UART
• Synthesis of a UART with Xilinx Webpack
• Layout library and extension
• Generating structural VHDL with AnalyzeJS.html
• Synthesis of a UART with Electric VLSI Design System
• Summary

Timeline

• UART basic run
• Generated VHDL Synthesis File with ISE Webpack: 1 h
• Transfer VHDL code with AnalyzeJS: 1 h
• Start Electric and load library sclib and create uartx: 1 h
• Total: 3 h
• Verification
• Verify Electric primitive cells versus VHDL code: 8h
• Verification of UART in ISE Webpack: 1h
• Verification of UART in LTSPICE: ??

VHDL description of a UART

• Modulo m counter: list_ch04_11_mod_m.vhd
• FIFO: list_ch04_20_fifo.vhd
• Test FIFO: list_ch04_21_fifo_test.vhd
• Button debouncer: list_ch06_01_02_debounce.vhd
• UART receive circuit: list_ch07_01_uart_rx.vhd
• list_ch07_02_flag.vhd
• UART transmit circuit: list_ch07_03_uart_tx.vhd
• Combine receive and transmit: list_ch07_04_uart.vhd
• Build a UART test circuit: list_ch07_05_uart_test.vhd
• Simulate operation of UART: sim_uart.vhd
• Electric VHDL: Electric_uart_test_synthesis.vhd

Xilinx Webpack UART

Analysis of synthesis file modulo_10_counter

.include cmosedu_models.txt
VDD VDD 0 DC 1
VCLK CLK 0 PULSE(0 1 9n 1n 1n 9n 20n)
VRST RESET 0 PULSE(0 1 50n 1n 1n 20n 20m)
.tran 1000n

Test of primitives

Simulation results of primitives

Analysis of synthesis file UART

AnalyzeJS.html Javascript

LUT3 and LUT4

entity LUT4_0DF0 is port( I0,I1,I2,I3: in STD_LOGIC;O: out STD_LOGIC);
end LUT4_0DF0;
architecture LUT4_0DF0_BODY of LUT4_0DF0 is
component LUT20 port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
component LUT2D port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
component LUT2F port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
component MUX4 port(I0,I1,I2,I3,I4,I5 : in STD_LOGIC;O: out STD_LOGIC); end component;
signal y1,y2,y3,y4,O2 : STD_LOGIC ;
begin
LUT2_1: LUT20 port map (I0,I1,Y1);
LUT2_2: LUT2F port map (I0,I1,Y2);
LUT2_3: LUT2D port map (I0,I1,Y3);
LUT2_4: LUT20 port map (I0,I1,Y4);
MUX0: MUX4 port map (Y1,Y2,Y3,Y4,I2,I3,O);
end LUT4_0DF0_BODY;

entity LUT3_6A is port( I0,I1, I2: in STD_LOGIC;O: out STD_LOGIC);
end LUT3_6A;
architecture LUT3_6A_BODY of LUT3_6A is
component LUT26 port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
component LUT2A port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
component MUX2 port (I0,I1,I3: in STD_LOGIC;O: out STD_LOGIC); end component;
signal y1,y2,O2 : STD_LOGIC ;
begin
LUT2_1: LUT2A port map (I0,I1,Y1);
LUT2_2: LUT26 port map (I0,I1,Y2);
MUX0: MUX2 port map (Y1,Y2,I2,O);
end LUT3_6A_BODY;

Electric

• Copy all LUT entities into VHDL text
• Copy entity of main uart into VHDL text
• Copy all components into architecture of main uart
• Remove the preset for pins clk, reset, rx in the entity port section
• Remove the ; after the last pin in the entity port section
• Remove entity FDC0, LUT12 and replace LUT12 usage with IBUF

Synthesis Results

Synthesis Results Layout

Verification with VHDL Simulation of UART

Verification with LTSPICE Simulation of UART

Conclusion and Outlook

Conclusion

• Success generating a layout from VHDL
• Most area is used with M1 wiring, since only 2 metal layers are available and supported by the routing tool.
• LTSPICE simulation could not be finished.

Outlook

• Investigate impact of routing rules and number of rows on area
• The layout has to be packed into a chip frame with input and output buffers.
• Investigate maximum number of transistors for ralistic LTSPICE simulation time.