Open Laboratory 2016: mod_m_counter

Build a minimum power consumption, minimum area and maximum clock rate mod_10_counter with minimum size 50nm transistors.

Generate VHDL for a mod_10_counter
Simulate and synthesize a mod_10_counter
Measure area, power consumption and maximum clock rate of the mod_10_counter with RCX.
Optimization:

Optimize VHDL code
Replace a MUX4 cell with an optimized MUX4 cell.

Measure and compare area, power consumption and maximum clock rate of the old and new mod_10_counter with RCX.

Check functionality and performance with simulations.

Tool chain

A VHDL description of a mod_10_counter is mapped to logic blocks using Xilinx ISE webpack.
The VHDL description is modified for Electric VLSI system using AnalyzeJS.js.
A standard cell library sclib.jelib is used with VHDL code to synthesize a mod_10_counter.

mod_10_counter VHDL

Start ISE WEbpack and create a new project with counter VHDL code.
Select File -> New Project; Set Name: "Counter"; Top-level source type should be HDL; Next;
Project Settings: Family Spartan3E; Device: XC3S250E; Package CP132; Preferred Language: VHDL; Next; Finish
In the Design tab Hierarchy window (top-left) right click mouse and Add Copy of Source: list_ch04_11_mod_m.vhd
Double click on the module opens the source code. Inspect the source code.

Create VHDL for synthesis of a layout

In the Design tab choose View: Implementation.
In the Process window (center-left) open the submenu of Synthesize - XST by clicking on the plus sign and start the process Generate Post-Synthesis Simulation Model.
This creates a structural VHDL code file in a subfolder: netgen/synthesis/mod_m_counter_synthesis.vhd
This file will be used later for synthesis of a layout.

Simulate behavior

In the Design tab choose View: Simulation.
In the 'Design' tab Hierarchy window (top-left) right click mouse and do 'New Source'.
Select 'VHDL Test Bench' and 'File name': test_count; Next; choose mod_m_counter; Next; Finish;
Open test_count file with a double click.
There is a section '-- insert stimulus here' and apply the reset signal for 100 ns.

      -- insert stimulus here 

      wait for clk_period*10;

      reset <= '0'; wait for 100 ns;
      reset <= '1'; wait for 100 ns;
      reset <= '0'; wait for 100 ns;

Select test_count.
In the Process window (center-left) open the submenu of ISIM Simulator by clicking on the plus sign and start 'Simulate Behavioral Model'.
ISim is starting and the signals are displayed.
Document the results.

Process VHDL

Start AnalyzeJS.html to be able to process Xilinx VHDL. Copy your netgen/synthesis/mod_m_counter_synthesis.vhd file into the input box.
Press 'Update source and process it'.
Open Electric VLSI Design System.
Open library sclib.jelib
Create new cell: View: VHDL; Name mod_m_counter.
Copy the "Entities" section from AnalyzeJS into the window.
Copy from "Processed output" section starting with line entity from AnalyzeJS into the window below the entities.
After the line "architecture Structure of mod_m_counter is" and before signal copy the section "Components" from AnalyzeJS.
Modify the presets of clk and reset in the entity.
Remove ; after last port.
If there are entities FDC0 or LUT12:
Remove entity FDC0 since it is not used.
Remove entity LUT12 and replace LUT12 usage with IBUF.

Synthesize Circuit and Simulate

Select M1 in another cell to enable the right layers for routing.
Select mod_m_counter{vhdl}.
Tools-> Silicon Compiler -> Convert current cell to layout.
For simulation create a new cell mod_m_counter doc.waveform.
In the tab 'Components' place the cell mod_m_counter layout.
Add the LTSPICE simulation text:

.include cmosedu_models.txt
.global VDD
VDD VDD 0 DC 1
VCLK CLK 0 PULSE(0 1 0 1n 1n 19n 40n)
VCLR RESET 0 PULSE(0 1 0 1n 1n 99n 2000n)
.tran 1000n

Do a LTSPICE simulation to check functionality.
Since the top level cell needs some inputs modify the line

*** TOP LEVEL CELL: mod_m_counter{doc.wave}
Xmod_m_co@0 clk gnd max_tick q__0 q__1 q__2 q__3 reset vdd mod_m_counter

accordingly.
Document your simulation result.
Repeat simulation with RCX extraction.

Optimize VHDL code and the cells for a LUT4 table

Investigate the used LUT4 and LUT2 circuits and replace at least one of them with an improved layout according to the rules in the class.
Investigate the structural VHDL. Can you optimize the VHDL code?
How much improvement in area, power consumption and maximum clock frequency can you achieve?
Document your results.

Synthesize a mod 200 and 1000 counter

Investigate maximum clock frequency and power consumption of a mod 200 and 1000 counter.
Modify N and M in the generic section of the mod_m_counter.

Deliverables

Document your laboratory in a pdf document with a name of < Date > _2016_Mod_ < name > .pdf and send it to joerg.vollrath@hs-kempten.de.
A maximum of 2 students can prepare a document together clearly marking authorship of different sections. Submission is due 10.7.2016.

Optimized Electric VHDL code
ISIM Simulation of start and optimized VHDL code
< Name > .jelib with modulo_10_counter, modulo_200_counter, modulo_1000_counter layout and simulation code
Improved layout of basic cell(s).
LTSPICE RCX simulation netlist of one layout
LTSPICE simulation result

Maximum delay
Power consumption at various clock frequencies

Table with area, power consumption, maximum clock speed of counters