Hochschule Kempten      
Fakultät Elektrotechnik      
Microelectronics       Fachgebiet Elektronik, Prof. Vollrath      


13 Faults and Test in Microelectronics

Prof. Dr. Jörg Vollrath

12 Power, Clock, IO

Video of lecture 13 (26.05.2020)

Länge: 1:01:57
0:0:0 Layout NCC checking transistor sizes

0:0:35 Silicon compiler layout result

0:3:48 Laboratory layout

0:6:31 M2 line

0:10:15 Silicon compiler result

0:13:44 Number of metal layers of a logic chip

0:16:10 Area of design styles

0:21:10 Design for test

0:23:13 Yield

0:28:16 Test

0:33:25 Test a truth table

0:34:43 Faults: Stuck at, bridging, transition

0:37:10 Layout and defects

0:43:10 Model of fault and defect sizes

0:45:0 Wafer maps

0:47:21 Defects and faults, fault coverage

0:52:41 Modeling defects: R and C#

0:54:13 Classical fault model

0:56:53 Timing delay fault

0:58:18 Process variations

1:0:35 Guard band

1:1:45 Memory test flow

1:5:37 Memory tester and handler



Today Test:

Test environment

Input vector, DUT, output vector
Picture memory wafer and component tester


Minimize test cost and maximize test coverage.
Do I have to test the complete state/truth table?
What is the root cause of a failure?
How can I optimize a process and a design to optimize yield?
Relating defects to fault models and electrical failures!

Yield for Memories

Number of good chips divided by total number of chips

Absolute yield numbers:
Relative yield number
Test sequence limited Yield YTSLY
Total yield: Y = Ys*YTSLY

Number of test

For small logic circuits the whole truth table can be tested.
For large logic circuits the number of input combinations increases exponentially.
Reduction of test vectors using fault models and structural information

Example: NAND
000 1This is tested with vector 1 and 2 and can be omitted
101 1
210 1
311 0
VN = 2IN · 2IREG
VN: number of input vectors
IN: number of inputs
IREG: number of registers


Fault modeling

Layout and Defects

  • Shorts in a layer
    • Source and Drain can be shorted by metal1
    • Gate short with polysilicon
  • Short between contact and adjacent line
  • Opens in layer
  • No adjacent lines a and c, no shorts possible

The layout influences the probability of shorts caused by defects

Faults, Layout and Defect size

  • Defect size and Layout rules have an influence on faults.
  • Defect model
  • Yield model

Defect wafer map

Same defect count can lead to different signatures

Defects and faults



S@0 stuck at 0
S@1 stuck at 1
Transition faults (TF)
Coupling faults (CF)

Realistic fault coverage
Fault coverage = Tested number of faults/ Total number of faults

Modeling Defects

Hard defects
Truth table
  • Short between lines
  • Opens in a line
Soft defects
  • Resistance
  • Capacitance

Classical Fault Model

S1S0 S1S0
00 0
01 0
10 0
11 1
S1S0 S1
00 0
01 0
10 1
11 1
S1S0 S1 + S0
00 0
01 1
10 1
11 1

A fault between S0 and S1.
A modified truth table for fault modeling is used.

Timing delay fault

Process and Operation point variations

Guard Band

Memory test flow

  • Temperature
  • Voltage
  • Yields
  • Guard band
  • Bins: physical slots for devices
  • Sorting: Data log which test failed first
  • Fail string: Pass fail information for each test

Memory tester and component handler

Pictures courtesy of Advantest Europe Gmbh
Shown is a memory tester with a workstation and a test head at the left.
This test head can be inserted to the component handler station on the right. Similar test heads are available for a wafer probe station.

Semiconductor Manufacturing


  • Semiconductor manufacturing
    Bosch, Infineon, Dialog, TI
  • EDA companies
    Mentor, Cadence, Synopsis
  • Semiconductor distributors
    Silica, AVNET
Research and Learning

Example: Mixed Signal IC

6 Digital design engineers, 3 analog design engineers, 3 test engineers, 2 support personnel
  • Digital design
    • $90k salary
    • $40k overhead
    • $10k computer
    • $10k CAD tools
    • Total: $ 150k * 6 = $900k
  • Analog design
    • $110k salary
    • $40k overhead
    • $10k computer
    • $50k CAD tools
    • Total: $ 210k * 3 = $630k
  • Fabrication
    • Back end tools: $1M/year
    • Masks: $1M/year
    • Total: $2M/year
  • Test Engineer
    • $90k salary
    • $40k overhead
    • $10k computer
    • $100k Test software
    • Total: $ 240k * 3 = $720k
  • Support staff
    • $50k salary
    • $20k overhead
    • $5k computer
    • Total: $ 75k * 2 = $150k
  • Summary
    • 2 years @ 4.5 M
    • $ 9 M design & prototype


  • Chip planning: Area estimation, yield, number of good chips
  • Cross section of an integrated circuit:
    • Layers, contact, active area, source, gate, drain, schematic
    • Devices: Resistor, capacitor, transistor, diode
  • Layout (Top view): Feature size
    • Layout <-> schematic
    • Design rules, logic density (gates per area)
  • Calculate
    • Resistance, capacitance, threshold voltage
    • Propagation delay
    • Power consumption, transistor sizing
  • Design and layout
    • Stick diagram
    • Good layout and cells
    • Design rules and standard cell layout guidelines
  • Circuits
    • Transistor characteristics
    • Logic: Inverter, AOI logic
    • Delay, setup and hold times
    • Memories and registers
  • Boolean function
    • Boolean function <-> truth table <-> schematic <-> layout<-> timing behavior
  • Read and write SPICE code:
    • Subcircuits, LTSPICE to block diagram and schematic
    • Identify nodes, inputs and outputs
    • Identify simulation mode, voltage sources, waveforms, models
  • Yield, defects, test, chips per wafer
    • Test: What is test?
    • Faults and fault models
    • Design for test