Microelectronics

13 Faults and Test in Microelectronics

Prof. Dr. Jörg Vollrath

12 Power, Clock, IO

Video of lecture 13 (26.05.2020)

Länge: 1:01:57

0:0:0 Layout NCC checking transistor sizes

0:0:35 Silicon compiler layout result

0:3:48 Laboratory layout

0:6:31 M2 line

0:10:15 Silicon compiler result

0:13:44 Number of metal layers of a logic chip

0:16:10 Area of design styles

0:21:10 Design for test

0:23:13 Yield

0:28:16 Test

0:33:25 Test a truth table

0:34:43 Faults: Stuck at, bridging, transition

0:37:10 Layout and defects

0:43:10 Model of fault and defect sizes

0:45:0 Wafer maps

0:47:21 Defects and faults, fault coverage

0:52:41 Modeling defects: R and C#

0:54:13 Classical fault model

0:56:53 Timing delay fault

0:58:18 Process variations

1:0:35 Guard band

1:1:45 Memory test flow

1:5:37 Memory tester and handler

Overview

Review:

Power calculation
Clock
Pads

Today Test:

Yield and faults
Defect oriented testing

Test environment

Input vector, DUT, output vector
Picture memory wafer and component tester

Users want to have only working integrating circuits. During manufacturing a lot can go wrong to cause obvious and subtle functionality problems.
Test screens bad devices.
Test cost can be up to half of manufacturing costs.
Test is no visible value added. Parts are sorted out as bad and not sellable.
This lecture looks at the area of test.

There is a yearly International Test Conference from the IEEE.

Test

Design for test
Logic Test
Test vectors
Memory test
Algorithmic pattern generator (ALPG) to test all memory cells
Built in self test (BIST)
Tester on chip
Wafer level test, burn-in test, component test
Defect oriented versus full test
Quality, diagnosis
Boundary scan and JTAG

Motivation:
Minimize test cost and maximize test coverage.
Do I have to test the complete state/truth table?
What is the root cause of a failure?
How can I optimize a process and a design to optimize yield?
Relating defects to fault models and electrical failures!

Yield for Memories

Number of good chips divided by total number of chips

$ Y = \frac{N_{Good}}{N_{Total}} $

Absolute yield numbers:

Contact yield: Y_cont Equipment and gross fails
DC Yield Y_DC: Standby and active current
Basic functional test (repairable): Screen yield Y_s
Write and read all cells
Perfect yield Y_s1

Relative yield number
Test sequence limited Yield Y_TSLY
Total yield: Y = Ys*Y_TSLY

Yield monitors the manufacturing process and ensures good product and maximum profitability.

Number of test

For small logic circuits the whole truth table can be tested.
For large logic circuits the number of input combinations increases exponentially.
Reduction of test vectors using fault models and structural information

Example: NAND

Nr	IN1	IN0	OUT
0	0	0	1	This is tested with vector 1 and 2 and can be omitted
1	0	1	1
2	1	0	1
3	1	1	0

For logic circuits basic functionality is ensured testing the state table or truth table.
This can take a lot of time and effort.
This is done in simulation and testing the final product at variuos steps.

V_N = 2^IN · 2^IREG
V_N: number of input vectors
IN: number of inputs
IREG: number of registers

Fault Types

Stuck at fault (SA) “0” or “1” (Logic, array)
short to fixed voltage potentia l
Bridging faults (BF) (Logic, array)
short between lines
Transition faults (TF)
A change of an input is not generating a change in output
Coupling faults (CF) (Array)
short between cells: Write to one cell influences the other cell
Pattern sensitive fault (PSF) (Array)
RAMs: refresh sensitive faults (Array)
Timing faults

Defining fault types structures the task of test and yield optimization.

Fault modeling

Defects: Open, short
Transistor faults: short between terminals
Node stuck at faults: '0', '1'
Transistion delay faults: '0' -> '1', '1' -> '0'
Truth table based faults
Path delay faults

Layout and Defects

Shorts in a layer

Source and Drain can be shorted by metal1
Gate short with polysilicon

Short between contact and adjacent line
Opens in layer
No adjacent lines a and c, no shorts possible

The layout influences the probability of shorts caused by defects

The picture shows a simplified model of defects on a layout.
A remaining metal1 particle shorts the drain and sourc of the upper left PFET.
A polysilicon particle shorts the polysilicon lines of the NFETs from inputs a and b.
A direct short of polysilicon lines from input a and c is not possible without involving polysilicon of input b.
This can have an impact on the necessary test pattern for the inputs.

Faults, Layout and Defect size

Defect size and Layout rules have an influence on faults.
Defect model
Yield model

Defect wafer map

Same defect count can lead to different signatures

Defects and faults

Defects

Faults

S@0 stuck at 0
S@1 stuck at 1
Transition faults (TF)
Coupling faults (CF)

Realistic fault coverage

Fault coverage = Tested number of faults/ Total number of faults

Modeling Defects

Hard defects
Truth table

Short between lines
Opens in a line

Soft defects

Resistance
Capacitance

Classical Fault Model

Wired-And

S1	S0	S1S0
0	0	0
0	1	0
1	0	0
1	1	1

Dominant

S1	S0	S1
0	0	0
0	1	0
1	0	1
1	1	1

Wired-Or

S1	S0	S1 + S0
0	0	0
0	1	1
1	0	1
1	1	1

A fault between S0 and S1.
A modified truth table for fault modeling is used.

Timing delay fault

Process and Operation point variations

A CMOS process has some variations

Lateral dimension
Layer thickness

Electrical parameters are influenced

Therefore SPICE models for worst case are generated
Low and high Vt MOSFET, short and long channel MOSFET

A device can be operated at

Low and high voltage
Low and high temperature

Timing simulation has to be done for all worst case operation conditions to ensure functionality
Process window lots are manufactured to look at process robustness

Guard Band

Memory test flow

Temperature
Voltage
Yields
Guard band
Bins: physical slots for devices
Sorting: Data log which test failed first
Fail string: Pass fail information for each test

Memory tester and component handler

Pictures courtesy of Advantest Europe Gmbh

Shown is a memory tester with a workstation and a test head at the left.
This test head can be inserted to the component handler station on the right. Similar test heads are available for a wafer probe station.

Semiconductor Manufacturing

Development of a new process
Testchip: device optimization
Yield learning
Qualification
Development of a new product
Design: Circuit, pads, test structures
Verification
Qualification
Manufacturing of a new product
Monitoring yield
Root cause analysis
Improvements

Opportunities

Work:

Semiconductor manufacturing
Bosch, Infineon, Dialog, TI
EDA companies
Mentor, Cadence, Synopsis
Semiconductor distributors
Silica, AVNET

Research and Learning

MOSIS
Europractice
Fraunhofer
Books
CMOS, VHDL
Conferences
JSSCS, SSCS, DATE, ITC, ESSCIRC
Internet Links
EDA Cafe
PLD Designline
efabless (Chip design)

Example: Mixed Signal IC (2010)

6 Digital design engineers, 3 analog design engineers, 3 test engineers, 2 support personnel

Digital design

$90k salary
$40k overhead
$10k computer
$10k CAD tools
Total: $ 150k * 6 = $900k

Analog design

$110k salary
$40k overhead
$10k computer
$50k CAD tools
Total: $ 210k * 3 = $630k

Fabrication

Back end tools: $1M/year
Masks: $1M/year
Total: $2M/year

Test Engineer

$90k salary
$40k overhead
$10k computer
$100k Test software
Total: $ 240k * 3 = $720k

Support staff

$50k salary
$20k overhead
$5k computer
Total: $ 75k * 2 = $150k

Summary

2 years @ 4.5 M
$ 9 M design & prototype

Competencies:

Chip planning: Area estimation, yield, number of good chips
Cross section of an integrated circuit:

Layers, contact, active area, source, gate, drain, schematic
Devices: Resistor, capacitor, transistor, diode

Layout (Top view): Feature size

Layout <-> schematic
Design rules, logic density (gates per area)

Calculate

Resistance, capacitance, threshold voltage
Propagation delay
Power consumption, transistor sizing

Design and layout

Stick diagram
Good layout and cells
Design rules and standard cell layout guidelines

Circuits

Transistor characteristics
Logic: Inverter, AOI logic
Delay, setup and hold times
Memories and registers

Boolean function

Boolean function <-> truth table <-> schematic <-> layout<-> timing behavior

Read and write SPICE code:

Subcircuits, LTSPICE to block diagram and schematic
Identify nodes, inputs and outputs
Identify simulation mode, voltage sources, waveforms, models

Yield, defects, test, chips per wafer

Test: What is test?
Faults and fault models
Design for test

Finish

Trial exam
Feedback: Interesting, fun, learning outcome?

Microelectronics

2019 05 14 13 Faults and Test Microelectronics Prof. Dr. Joerg Vollrath

Microelectronics

13 Faults and Test in Microelectronics

Prof. Dr. Jörg Vollrath

Video of lecture 13 (26.05.2020)

Overview

Test environment

Test

Yield for Memories

Number of test

Fault Types

Fault modeling

Layout and Defects

Faults, Layout and Defect size

Defect wafer map

Defects and faults

Faults

Modeling Defects

Classical Fault Model

Timing delay fault

Process and Operation point variations

Guard Band

Memory test flow

Memory tester and component handler

Semiconductor Manufacturing

Opportunities

Example: Mixed Signal IC (2010)

Competencies:

Finish