Hochschule Kempten      
Fakultät Elektrotechnik      
Microelectronics       Fachgebiet Elektronik, Prof. Vollrath      

Microelectronics

12 Power, Clock, IO, Microelectronics

Prof. Dr. Jörg Vollrath



11 Memories




Video of lecture 12 (19.05.2020)


Länge: 1:01:57
0:0:0 Microelectronics

0:0:59 Story complex systems

0:5:30 Test

0:7:5 Power equations

0:10:26 Power, VDD, delay

0:12:5 DRAM IDD Specification

0:15:46 Dynamic current analysis

0:19:2 Ring oscillator

0:22:24 Bypass capacitances

0:24:42 Power grid

0:27:16 Internal voltages power on sequence

0:32:26 Power system model

0:35:54 Memory chip package

0:37:54 Clock

0:38:39 Clock distribution

0:43:7 Clock examples

0:45:46 Package

0:49:19 Package parasitics

0:50:13 SPICE simulation and measurement

0:53:23 Input and outputs

0:59:15 FPGA IO pads

1:0:36 Chip with pads

20.5.2020 Review of laboratory status

You should not use M3 or M2-M3 contacts.
Load and source should be comparable to input capacitance and output resistance of DUT cell.
Make versions of your cell: Duplicate with name and version number.
Transistor size in schematic and layout should match.
Tools-NCC-Schematic and layout
File-Preferences-Tools-NCC-Check transistor sizes
Select metal2 and the draw a line in M2.
Exports should be in M1-M2 contact.
Measurements statements can be included in the LTSPICE file and results are written in a log file.
Placing a contact does not yet make connection. You have to do it afterwards by connecting lines.

Overview

Review:

Today:

Microelectronics story

How to build complex systems and plan progress


Power


Instantaneous power
P = v(t) · i(t)
Average power
Pavg = V · I = VDD Iavg

\( C = \frac{Q}{V} = \frac{I \cdot t }{V} \)
\( I = \frac{C \cdot V}{t} = C \cdot V_{DD} \cdot f_{CLK} \)
\( P_{act} = C \cdot V_{DD}^2 \cdot f_{CLK} \)

Power discussion


Power and Speed


VDD [V]Pavg [mW]E [pJ]Delay [ns]
0.8 89.2 356 1.568
0.9 114 455 1.335
1.0 142 566 1.178
1.1 173 693 1.068
1.2 209 837 0.987
Performance of a semiconductor process can be measured using a ring oscillator.
The ring oscillator connects the output of an odd series of inverters with the input creating an unstable feedback.
The oscillator frequency is limited by the propagation delay of the inverters.
This measures the RDSon, Cin and ft.

DRAM IDD Specification


Micron 256Mb DRAM -5B, VDD = 2.6 V, MT46V32M8
Operating one-bank precharge currentIDD0= 75 mA
Operating one-bank active-read-precharge currentIDD1= 85 mA
Precharge power-down standby currentIDD2P= 4 mA
Idle standby currentIDD2P= 23 mA
Auto refresh burst currentIDD5= 115 mA
Operating bank interleaved read currentIDD7= 175 mA
There is a great variation in current. Receiver and driver circuits can be turned on and off.
The voltage has to be stable for all conditions.

Dynamic power peaks and currents


  • Standby
  • Active:
    Read, write, compute
  • Power on, power off

DRAM dynamic read current


Ring oscillator power buffering with bypass capacitors


Simulation:
A ring oscillator shows the performance of a given semiconductor technology.
A 50 nm simulation shows a frequency of 500 MHz.
Series resistance in the power lines limits the voltage swing between 80 mV and 900 mV.
Average current is 93 mA.
The voltage level of gnd and vdd shows a ringing due to changing IDD.
Bypass capacitors can reduce the swing on the power lines, given more stable operation.
Not used area on chip can be filled with capacitance.

Real bypass capacitors


Frequency response of power capacitances:
A real capacitance has a parasitic resistance and inductance.
There is a limited bandwidth for supply voltage stabilization.
A combination of many capacitances with optimized resistance and inductance is needed.

Power grid: DRAM example


There are separate power supply pins for the data input and outputs (IO).
The number of power pins is proportional to the number of IOs.
There are separate grids for digital and analog circuits.
Horizontal and vertical lines are connected to a grid and provide power.

The block diagram shows different voltages in different colors in different areas.
Voltage pumps and regulators are shown in grey.
A bandgap reference circuit provides temperature and voltage independent voltages.

Power on sequence: DRAM


DRAM internal voltages and power on sequence.
A low array voltage is used to save power.
A negative back bias is needed reducing memory cell leakage current.
A high voltage Vpp gives the select transistor overdrive to store the full Vblh level in the memory cell.
Vint is optimized for speed and to be able to drive the IOs.
A high current peak, when power is turned on, has to be avoided.
All capacitances will be charged up at power up.

Power system model

  • Power management and power supply
  • Printed circuit board (PCB)
  • Package
  • Chip

Memory chip package

This is a TSOP5 package used around 2005 for DRAM memories.
Nowadays memories use bga packages.
The package is smaller and has better high speed performance. It is more expensive than a TSOP package. Test and failure analysis is more difficult.

Clock

CLK Distribution: H-Tree and clock domains

H Tree
System on chip
Microprocessors have one central clock distributed via a balanced or unbalanced H-tree.
Systems on chip have many blocks with local clocks.
Communication is done via serial bus between clock domains.
Divide and conquer.

Power and clock Example


Package and Pads

  • The package limits chip size, maximum heat, frequency (parasitics), price, number of pins, input capacitance and inductance.
  • Matching of measurement and simulation makes sure all parasitics are understood.
  • Package development and qualification is part of chip development
  • Package filler material can damage the chip
  • Package prevents chip damage via moisture or physical strain.
  • Power distribution, voltage drop, buffer capacitances and noise.
  • Pads: power, input, output
  • Pad circuits are supplied by the manufacturing facility in the design manual.
  • Pad simulations have to be done at the 3-D device simulation level and are not very accurate.
Dual in line (DIL)

Thin small outline (TSOP)

Ball grid array (BGA)

Package parasitics

Bond wires


Gold bond wires connect the chip pads with metal lead frame.
Thermal coupling is also achieved with bond wires and lead frame.

Model:

Inductance
Capacitance
Resistance

SPICE simulation and measurement

Input and Outputs (IOs)

IO pads and pins in VHDL

User constraint file (.ucf)
  • .ucf
  • Pin name and signal name
  • Timing constraints
Pin specification
  • Voltage level
  • TTL, CMOS
  • Tristate
  • Termination resistor

References

Laboratory: TinyFPGA
2018 TinyFPGA

Electric libraries:
muddpads13_ami05.jelib
pads4u.jelib
Electric: Tools -> Generation -> Pad frame generator
A configuration file (*.arr) allows automatic pad generation. Wiring can then be done with the Sea of gates route.
In the user manual an example is provided.

This example shows the pad frame not the active area to limit minimum chip size.
Alignment marks and labels for chip identification are missing.
Multiple chips are put on one reticle with a distance of 200 µm for sawing (dicing) to separate the chips.
Test structures are placed in this space to be able to monitor process performance.


MOSIS 0.35 µm IO Pads
MOSIS 0.35 µm IO Pads

Summary

Next: 13 Faults and Test