Microelectronics2020 VideosProf. Dr. Jörg Vollrath |
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Video of Lecture Introduction
Video of Lecture 01 Introduction 20.3.2020
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Duration: 51:27 min |
4:20 Webpage 6:40 Laboratory 8:23 Problems, Exams 11:00 A Chip 12:00 Introduction 12:42 Lecturer 13:39 Background 15:10 Area: Electronics 16:30 Course Content 17:40 Wikipedia: Microelectronics 19:00 Relevance 20:57 Companies 23:56 Sales leader 25:52 Books 28:40 Exam and Grading 30:22 Transistor Evolution 33:53 Moores Law 36:46 Feature Size 37:24 Size of transistor 45:08 Feature size graph 48:29 Finish 50:00 Exams |
Video of Lecture 2 Electric
Electric, LTSPICE: Simulation of a NFET, design of a layout 25.3.2020
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Länge: 1:04:23 |
0:43 Task create transistor 1:55 Bottom up approach 2:40 Take notes 3:47 Open Laboratory 1/2 web page 4:09 Electric configuration 4:22 Preferences 4:55 Maximum memory, maximum permanent space 5:17 Technology: mocmos, 6 Layers 6:01 Scale: λ = 500nm, Feature size F = 1000nm 7:35 Mark all libs 7:50 Color Scheme: White Background 8:20 Tools, Simulation, Spice 9:15 preferences: Run Spice 9:40 Command line for LTSPICE: program LTC\LTspiceXVII\XVIIx64.exe
or program (x86) LTC\LTspiceIV\scad3.exe 11:20 Insert quotation marks. 13:40 Arguments for spice 14:24 Working result directory 15:50 Web page laboratory 1/2 16:47 Export Preferences Start simulation of NMOS transistor schematic 17:52 Start simulation of NMOS transistor 18:15 file copy: cmoesedu_models.txt, Lab01_1u_00.jelib 19:20 File open library 17:52 Start simulation of NMOS transistor 20:00 Electric messages 23:38 EDA explanation, tabs 24:00 Explorer, library, NFET schematic 24:33 NFET transistor pins and LTSPICE code, size 25:48 Transistor model 26:23 Voltage sources 26:42 Set Spice model 27:14 Insert LTSPICE text 28:00 Voltage sources, nodes and names 28:50 Transistor model, simulation statement 29:23 Start Spice simulation 29:40 error .option nopage just delete the options line 30:59 Schematic view 37:25 SPI file, no schematic, only netlist 37:53 run, remove .options line 38:28 add trace: show simulation curves 39:00 Output characteristic of a NFET Start layout 40:14 Create layout cell 41:10 Components 41:45 NMOS transistor layout 42:26 NMOS width and length 43:26 NMOS SPICE model name 42:43 Cycle selection 44:26 NMOS drain and source 44:50 NMOS gate polysilicon contact 45:10 Make connections 45:40 Export gate 46:50 Make connections 50:50 NFET source, drain 51:25 Connection 52:30 Resize 52:50 Design rule error 53:20 Drain export 55:40 Bulk pwell contact 56:35 SPICE text 57:00 SPICE simulation 57:20 Add trace 57:40 Voltage source VS node missing 58:40 File, save plot settings 59:30 Verifiy fix 1:01:35 Save active library |
Video of Lecture3
Video of Lecture 03 MOSFET 31.03.2021
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Duration: 51:27 min |
0:0:0 LTSPICE Help MOSFET 0:2:3 LTSPICE presentation 0:6:15 .dc simulation 0:7:8 transfer curve 0:8:30 50nm simulation 0:10:30 scaling factor 0:11:30 1um feature size in layout 0:13:3 threshold voltage 0:15:15 Maximum voltage 0:15:45 Verification 0:16:10 PMOS Layout 0:17:45 PFET 0:20:45 LTSPICE presentation 0:22:7 Blessing and curse 0:23:51 Design entry 0:25:6 Design first time right 0:26:9 Find one solution 0:30:25 Design flow 0:31:1 Technology comparison 0:32:49 MOSFET Transistor 0:33:43 Transistor curves 0:35:23 Vth, λ, current 0:36:53 Maximum voltage 0:37:44 Inverter 0:38:28 Source, drain defined by voltage levels 0:39:11 Matching schematic and layout 0:41:43 Abstractions and conversion 0:42:23 Maximum current 0:43:43 Weak inversion 0:46:3 Bulk, well voltage changing threshold voltage 0:49:15 Typical MOSFET layout with unit transistors 0:54:50 Transistor parameters 0:58:43 Example of 130nm technology transistor parameters 1:5:42 QA: Electric delete a connection 1:7:21 Design rule check 1:8:24 QA: Parallel and series transistors 1:8:58 QA: Varying colors for gate, metal, source, drain 1:9:59 Area for one transistor 1:14:48 3D View 1:16:15 How to work 1:17:30 VW is a well |
Video of Lecture 04 Inverter
Video of lecture 04 Inverter 1.4.2020
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Länge: 01:25:00 |
0:0:0 Start Chip Opamp 0:1:55 Chip 0:3:20 Questions 0:6:54 PFET 0:8:8 LTSPICE 0:13:41 Layout PFET 0:22:18 Layout Simulation 0:25:28 Electric SPICE model 0:26:49 Chip layout 0:33:4 MOSFETs 0:35:24 Inverter 0:38:20 MOSFET as switch 0:39:38 Inverter, Transmission gate 0:42:13 MOSFET model with R and Cox 0:44:33 Propagation delay 0:46:53 Inverter 0:47:51 Transfer curve 0:50:20 Switching of inverter 0:53:41 Elaboration Delay 1:6:1 Standard cell layout 1:13:38 Individuell laboratory report until 15.4.2020 1:16:8 Copy, paste, modify 1:21:0 Pass gate, transmission gate 1:22:8 Limited voltage of a pass gate |
Video of Lecture
Video of Lecture 05 IC Manufacturing 7.04.2020
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Länge: 00:37:57 |
0:00:20 NMOS/PMOS size 0:01:25 Where is VB? 0:03:45 STI 0:04:06 IC manufacturing 0:05:16 Status manufacturing 2017 28nm and 14 nm 0:08:00 Wafers and Lots 0:10:35 Wafer map 64 MBit 0:14:09 Yield 0:17:13 Defect density 0:21:57 Relative yield 0:25:20 DRAM memory chip 0:27:05 Cross-section of a chip 0:29:25 Process steps 0:33:10 Polysilicon 0:34:59 Contact holes |
Video of Lecture
Video of Lecture 06 Design Rules 8.4.2020
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Länge: 01:02:59 |
0:0:34 PFET simulation not working 0:1:16 Be precise 0:2:21 Error message 0:3:50 Debugging 0:4:40 Netlist 0:6:50 Netlist PFET 0:8:20 Voltage sources 0:9:30 Simulation command 0:11:37 How does VB affect Id 0:12:32 Required width and length 0:15:20 Design rules 0:17:14 Wafer carcass 0:20:40 Reverse Engineering, competitor analysis 0:24:48 iPhone analysis 0:26:23 Design of a chip: schematic, layout, stick diagram 0:29:35 Mosis design rules 0:33:30 Design rule check DRC 0:37:35 Schematic versus Layout NCC 0:38:50 Mosis 0:39:38 From Circuit to chip 0:40:40 Inverter mask set 0:43:28 Pattern transfer 0:47:19 Overetch 0:49:30 Underexposure 0:51:28 Design rule check example 0:53:45 Overlap 0:56:25 Layout to schematic to truth table |
Video of Lecture
Video of Lecture 07 RLC in Microelectronics 14.4.2020
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Länge: 1:11:13 |
0:00:50 Devices outline 0:03:38 Resistance 0:05:38 Doped silicon resistance 0:07:30 Sheet resistance 0:10:19 Layout of resistor 0:12:11 Contact resistance 0:13:38 Electromigration 0:16:15 Supply voltage 0:19:02 Capacitances 0:21:10 Example resistor 0:24:43 Inverter parasitics 0:31:00 Example metal over poly 0:32:20 - Squares for C 0:33:10 - Fringe capacitance 0:34:00 - Capacitance calculation 0:36:15 - Resistance 0:38:10 - Voltage drop 0:39:30 - Cross section 0:42:15 - Metal 0:44:10 MOSFET C,R, Diode, bipolar transistor 0:48:05 Schematic to layout via stick diagram 0:51:50 AOI design style 0:58:40 Sum of products schematic 1:02:45 Multiplexer, demultiplexer 1:05:27 4 input truth table implementation with LUT2 and MUX 1:08:28 Tri-state driver |
Video of Lecture
Video of Lecture 08: Laboratory CMOS inverter 15.04.2020
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Länge: 1:28:22 |
0:1:30 Summary table 0:3:30 References 0:4:0 Text for graphs 0:6:10 Describe problems 0:7:20 Vth values 0:8:30 Screenshots LTSPICE, netlist text copy 0:10:0 Abstract, Internet news 0:12:0 Netlist transistor W, L, model 0:13:35 Curve fitting for MOSFET 0:19:30 Lab 3/4 start 0:20:50 Open library 0:23:40 Check design rules 0:24:12 Inverter_1x3 layout explanation 0:26:20 Size of Mosfet 0:27:10 Task like at work 0:27:50 Preferences, technology scale, 25nm 0:29:40 Different inverter designs 0:31:20 Investigate DC characteristics 0:32:0 Design a Inverter 9x1 0:34:0 Copy 3 times 0:34:45 Connect VDD, gnd 0:35:25 Inputs and outputs 0:36:30 Output connection with M2 0:37:0 DRC 0:39:10 DRC Error analysis 0:41:32 Redo it 0:42:0 Copy cells in group 0:43:55 Connect VDD, gnd 0:44:46 Connect inputs outputs 0:47:11 NCC layout vs schematic checking 0:48:50 Discussion moving of cells and wiring problems 0:50:15 NCC sizes not checked 0:51:10 Change ic view inverter name 0:52:20 Fix schematic 0:53:10 DRC schematic: Delete dangling arc 0:54:15 DC simulation 0:54:45 Eye tool to see cell content 0:58:0 Eye tool works on selection 0:58:45 LTSPICE simulation 0:59:0 Discussion netlist 1:0:0 Subcircuit discussion 1:1:50 Select displayed curves 1:2:30 Curve discussion 1:3:35 Layout inverter sizes 1:5:5 Change name in {ic} view 1:8:0 Insert Inv 9x1 into DC simulation 1:9:10 Make connections: VDD, gnd, in, out 1:10:40 Save library 1:11:35 Remaining task simulating delays 1:12:48 Create schematic from layout 1:14:0 Count number of transistors 1:15:20 Why do you make bigger transistors 1:16:40 Propagation delay 1:18:28 Transistor length and width 1:19:38 Length and width in netlist 1:21:3 cmosedu_models.txt and transistor models 1:22:25 Estimating tramnsistor sizes on paper 1:24:38 Channel length modulation lambda from measurements |
Measuring MOSFET parameters
Video of Lecture
Video of Lecture 08: Systems, Synthesis, VHDL 21.04.2020
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Länge: 1:30:00 |
0:1:0 Wafer diameter 0:5:6 n-well, Alignment 0:7:10 Number of chips per wafer 0:8:30 Contact resistance 0:10:25 Multiplexer truth table 0:13:30 Transistor design roll-off 0:17:0 70nm technology 0:18:30 Unit transistor 0:20:0 Standard cells 0:21:0 Unit transistor 1 bit adder 0:22:15 4 bit adder 0:23:50 Data path 0:24:45 Chip layout 0:27:10 Design entry for a chip 0:28:0 Electric LUT4_37E5 0:29:30 LUT4_37E5 truth table 0:31:0 Sum of products 0:36:50 Schematic to layout 0:38:0 Simulation LTSPICE 0:40:10 Silicon compiler 0:40:50 Delete subcircuits with layout in VHDL 0:42:15 Silicon compiler error number of rows: 1 row 0:43:0 Select metal 2 0:44:0 Where are instructions for silicon compiler 0:48:40 Optimize placing 0:50:0 Presentation of silicon compiler 0:51:0 Optimize routing distance 0:53:0 Layout simulation 0:54:15 Simulation with parasitics 'conservative RC' 0:57:50 What kind of isolation is used? 1:0:0 Inverter cross section isolation 1:1:25 Example C and R calculation cross section isolation 1:2:50 Schematic to layout summary 1:4:10 Number of wiring layers and area 1:6:45 Silicon compiler instructions 1:7:50 VHDL important things 1:9:30 Entity and architecture 1:12:40 VHDL in Electric 1:17:0 Internet page: NANDland 1:20:0 Netlist for synthesis: net.quisc 1:21:25 Three state driver 1:22:25 Hierarchy 1:23:45 Truth table and state machines 1:26:20 Libraries 1:26:50 Test signals in VHDL |
Video of Lecture
Video of laboratory review (22.04.2020)
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Länge: 1:30:00 |
0:0:59 Simulation error: Can't find definition of model N 0:2:38 LTSPICE file 0:3:10 Check for cmosedu_models.txt 0:4:30 Look at cmosedu_models.txt 0:5:40 Error: No metal2 layer visible 0:7:0 Visible layers 0:8:50 No output vout5 0:11:50 Export: Manipulate Export 0:13:25 Goal of laboratory 0:18:10 Vout5 missing 0:21:50 Vout5 shorted to Vdd 0:23:25 Delete M0 line 0:25:8 Status laboratory 0:30:0 No LTSPICE code in inverter 0:35:0 Voltage source overwritten by .dc simulation command 0:37:0 Sine amplifier simulation 0:39:10 AC simulation 0:45:40 N-FET model missing 0:57:0 Delay measurements Lab03/04 1:2:45 All transient output curves 1:3:58 Enable parasitics: Preferences, Tools, SPICE, conservative RC 1:7:0 Propagation delay 50% in 50% out 1:9:10 How to measure in LTSPICE 1:12:10 Measurement file 1:13:0 Run measurement file 1:17:20 Thick lines LTSPICE 1:20:0 Grading of laboratory 1:26:0 Documenting laboratory 1:29:0 Cursormeasurement |
Video of Lecture
Video of lecture 9 FPGA, Delay and Power (28.04.2020)
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Länge: 1:30:00 |
0:0:0 Review 0:1:35 Test input signals in VHDL 0:2:13 Behavorial VHDL to structural VHDL 0:5:15 Synthesis of UART 0:7:48 Start UART VHDL description from Book 0:9:20 Basic cells and simulation 0:10:50 UART basic cells 0:11:45 AnalysisJS.html Translation of VHDL 0:13:0 Synthesized layout 0:15:0 LTSPICE simulation to many transistors. 0:17:15 FPGA details 0:19:50 Lookup table in FPGAs 0:21:56 FPGA Books 0:23:15 Microelectronics design choices 0:25:40 Chip example: Gate array, standard cells, full custom 0:28:9 Propagation delay measurement: source, DUT, load 0:30:0 Propagation delay equation 0:34:0 Power consumption 0:40:0 Delay, load and W 0:46:28 Delay equation and graph revisited 0:50:0 Derivative to find minimum delay 0:53:30 Delay with multiple stages 0:55:50 Very high load can lead to multiple stages 0:57:40 Delay optimization in logic gates with series transistors 0:59:30 Propagation delay and pipelines 1:3:20 Insert registers |
Video of Lecture
Video of lecture 11 Area, D-Flip-Flop, State machine(29.04.2020)
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Länge: 1:30:00 |
0:0:0 Start measure times in LTSPICE 0:1:23 Rise and fall time 0:2:43 Measurement file statements for rise time 0:6:23 Area of one transistor 0:7:23 Area estimation 0:13:23 Area of one bit 0:15:23 Pipeline, propagation delay. maximum frequency 0:21:3 Microelectronics problems and exam 0:26:23 Microelectronic system design 0:34:32 Area estimation 0:36:23 MIPS R3000A cpu chip 0:38:53 Area estimation of chip 0:42:48 Book: The Pentium Chronicles 0:43:53 Looking at intel processor chips 0:46:3 D-Flip-Flop 0:49:13 D-Flip-Flop details 0:52:3 Qm is clk level triggered 0:55:23 Undefined state 0:56:43 Setup and hold time 0:58:43 Measuring setup and hold time 1:2:13 Shmoo plot 1:4:53 State machine (Medwedew) RTL register transfer language 1:7:23 Maximum clock frequency 1:8:53 Specification of state machine: state diagram and table 1:12:13 VHDL state machine |
Video of Lecture
Video of Lecture 10 Test and Scan cell (5.5.2020)
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Länge: 1:12:00 |
0:1:10 Plan 0:2:16 Last week 0:2:40 Test 0:5:6 Truth table and test 0:8:37 NAND Gate and errors 0:12:0 LTSPICE display of signals 0:15:10 Library and simulation 0:15:58 sclib and simulation cells 0:20:0 Pure logic test: static, dynamic 0:24:0 Stae machine test 0:25:35 Scannable D-Flip-Flop 0:27:40 Operation of scan cells 0:32:14 How to realize a scan cell 0:33:36 Schematic of a scan cell 0:35:0 Simulation of a scan cell 0:36:15 Documentation of test 0:38:50 TE active 0:39:40 Normal operation 0:41:50 Improved 0:43:50 TestJS: create LTSPICE test vectors 0:49:0 Explain simulation 0:52:33 LTSPICE online simulation 1:0:55 Number of needed test vectors 1:3:48 Example Tiny FPGA 1:6:50 Dynamic scan cell 1:9:0 Design automation inserting scan cells |
Video of Lecture
Video of laboratory design and synthesis (6.5.2020)
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Länge: 1:00:00 |
0:3:45 Delay Equation 0:4:0 Inverter delay reports Micro 0:6:0 Longest delay 0:7:18 Stop 0:8:50 Stage 1 delay 0:10:58 Stage 3 0:12:28 Stage 4 0:12:45 Stage 5 0:13:50 Stage 6 0:14:30 Stage 7 and 8 0:15:22 Stop 0:20:0 Synthesis Start 0:22:45 Specification 0:24:0 Schematic 0:26:30 First task 0:27:0 VHDL Synthesis start 0:27:45 Start Vivado 0:29:0 Expectation of features of tool 0:31:0 Behavioral VHDL code 0:34:0 Run synthesis 0:40:30 VHDL structural description 0:43:50 AnalyzeJS.html transfer Vivado structural VHDL output to Electric VHDL 0:46:50 Electric VHDL 0:50:0 VHDL files on web page 0:54:0 Open sclib.jelib before doing Silicon Compiler 0:58:0 Libraries 0:59:30 Tools Silicon Compiler (Error message) 1:0:10 Finish |
Video of Lecture
Video of lecture 11 Memories (12.05.2020)
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Länge: 1:10:08 |
0:1:55 Memories 0:2:20 Picture Processing 0:5:0 Memories in personal computers 0:6:0 Memory applications 0:8:40 Memory types 0:10:0 Memory array cells 0:14:56 Memory array 0:16:6 Memory LTSPICE circuit 0:18:39 DRAM layout 0:20:30 AA 0:20:50 Polysilicon 0:21:30 Contacts 0:21:56 metal lines 0:23:0 Contacts and capacitors 0:29:12 SRAM cell 0:33:33 Contacts 0:39:10 NAND Flash memory 0:47:55 Memory array 0:48:50 LTSPICE memory simulation 0:53:0 VHDL code ROM 0:57:20 DDR3 SDRAM Access 1:2:18 Summary 1:3:50 Limits of minimum feature size |
Video of Lecture
Video of laboratory (13.05.2020)
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Länge: 1:10:08 |
0:1:30 Delay Chain 0:2:30 Transition rise and fall 0:4:4 With RC parasitics and without 0:5:50 Delay dependence on input rise or fall time 0:7:40 Systematic investigation sorting 0:8:30 Graph 0:9:30 Influence of RC parasitics 0:10:40 Comparison 1x1 to 3x3 0:13:0 Realistic source and load 0:14:0 Delay tpdHL versus tpdLH 0:17:50 Sorting 0:23:0 Design strategy for a circuit 0:25:0 Area per transistor 0:27:40 Simulation with variations Vth 0:29:45 Open laboratory task 0:34:40 Simulation of cells 0:37:48 Cell a2o1_1x discussion 0:40:50 Power consumption 0:43:50 Open laboratory description 0:47:50 Plan of lectures 0:50:0 Area calculation 0:56:20 Testing the cell 0:58:0 Are there more tasks available 1:0:30 Use muddlib07.jelib cells as excercise 1:2:20 Exam SS 2012 problem 2 1:5:17 Area calculation 1:7:25 Lambda and feature size 1:13:0 AOI design style 1:15:45 Laboratory serial Gray to binary code synthesis 1:19:0 LTSPICE simulation 1:22:40 TestJS.html 1:26:30 LTSPICE output 1:27:10 Create Pad frame 1:28:20 Maze routing 1:29:10 Reticle |
Video of Lecture
Video of lecture 12 (19.05.2020)
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Länge: 1:01:57 |
0:0:0 Microelectronics 0:0:59 Story complex systems 0:5:30 Test 0:7:5 Power equations 0:10:26 Power, VDD, delay 0:12:5 DRAM IDD Specification 0:15:46 Dynamic current analysis 0:19:2 Ring oscillator 0:22:24 Bypass capacitances 0:24:42 Power grid 0:27:16 Internal voltages power on sequence 0:32:26 Power system model 0:35:54 Memory chip package 0:37:54 Clock 0:38:39 Clock distribution 0:43:7 Clock examples 0:45:46 Package 0:49:19 Package parasitics 0:50:13 SPICE simulation and measurement 0:53:23 Input and outputs 0:59:15 FPGA IO pads 1:0:36 Chip with pads |
Video of Lecture
Video of lecture 13 Design for Test and Faults(26.05.2020)
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Länge: 1:01:57 |
0:0:0 Layout NCC checking transistor sizes 0:0:35 Silicon compiler layout result 0:3:48 Laboratory layout 0:6:31 M2 line 0:10:15 Silicon compiler result 0:13:44 Number of metal layers of a logic chip 0:16:10 Area of design styles 0:21:10 Design for test 0:23:13 Yield 0:28:16 Test 0:33:25 Test a truth table 0:34:43 Faults: Stuck at, bridging, transition 0:37:10 Layout and defects 0:43:10 Model of fault and defect sizes 0:45:0 Wafer maps 0:47:21 Defects and faults, fault coverage 0:52:41 Modeling defects: R and C# 0:54:13 Classical fault model 0:56:53 Timing delay fault 0:58:18 Process variations 1:0:35 Guard band 1:1:45 Memory test flow 1:5:37 Memory tester and handler |