Outline

• Motivation and Objectives



AI, NPU calculations use floating point numbers



• Number formats and operations
  Posive integer, negative, fixed point, floating point
• Implementations
  Full adder, multiplier
• Tasks
  Truth table application
• Deliverables

Numbers and Number Formats

• Signed Integer: Sign, complement
  8 Bit: +127,0,-128
• Floating point: signed mantisse + exponent 8 Bit FP8 (E3M4): 1 Bit Sign, 4 bit significant, 3 Bit exponent
• Programming, calculation: NaN, +inf, -inf
• Posit8, Talkum8, Posits
• Base for exponent, mantissa: 2,3,4,5,8,(16,32)
• Operations and size of truth table:
  
  • Mapping decimal and number (Truth table size: 2^N)
  • Minus -x, Max/x (Truth table size: 2^N)
  • Add, multiply, power (Truth table size: 2^(2N))
• Notation: FPn EeMm (1.e.m) n = 1 + e + m
  Sign 1, exponent e, mantissa m
  FP8-E4M3 (1.4.3)
  

  Sign	Exponent				Significand Mantisse
  S	E	E	E	E	M	M	M
  0	1	0	0	1	0	1	1
  1.4.3

Minifloat

Machine learning

Operations

Size of truth table:

• Mapping decimal and number (Truth table size: 2^N)
• Minus -x, Max/x (Truth table size: 2^N)
• Add, multiply, power (Truth table size: 2^(2N))

Truth Table Operations 4-Bit

• Minus -x, Max/x
  16 codes
• Add, multiply, power
  256 codes
• Operation with NaN gives NaN
• Division with 0 gives +- infinity
• Division with infinity gives 0 or delta

Floating point calculation

 SEEM
 +010 :   1       
++001 :   0.5
---Fixed point--------
 +01.0 :   1.0  
++00.1 :   0.5 
---Add---------------- 
 +01.1 :   1.5
-- Floating point ---- 
 SEEM
 +011  :   1.5

FPU Intel 8087 8-Bit

Multi cycle serialization

Arithmetic truth table implementation

Truth table implementation

How many LUT2s and MUX2, MUX4 are needed for realization of a truth table?

(2026 Objective)

How many transistors are needed for a typical truth table?

2026 Objective

4-Bit Truth table Division

4-Bit Truth table Addder

4-Bit Truth table Multiply

Lookup table synthesis

-------------------- Cell div_0_jv{vhdl} --------------------
entity div_0_jv is port(I0, I1, I2, I3: in BIT; O0,O1,O2,O3: out BIT);
  end div_0_jv;

architecture div_0_jv_BODY of div_0_jv is
  component LUT20 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT21 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT22 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT23 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT24 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT25 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT27 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT2E port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT2F port(I0, I1: in BIT; O: out BIT);
    end component;
  component MUX2 port(I0, I1, I3: in BIT; O: out BIT);
    end component;

-- LUT2 signals
  signal net_0, net_1, net_2, net_3, net_4, net_5,  net_7, net_E, net_F: BIT;
-- First stage MUX2 outputs
  signal net_F7, net_F1, net_E1, net_32, net_54 : BIT;

-- Previous stage
--  signal net_O3aa, net_O3ab, net_O3ba, net_O3bb: BIT;
--  signal net_O2aa, net_O2ab, net_O2ba, net_O2bb: BIT;
--  signal net_O1aa, net_O1ab, net_O1ba, net_O1bb: BIT;
--  signal net_O0aa, net_O0ab, net_O0ba, net_O0bb: BIT;
-- Last stage
--  signal net_O3a, net_O3b, net_O2a, net_O2b, net_O1a, net_O1b, net_O0a, net_O0b: BIT;

begin
-- output3: 00F7

  LUT27_0: LUT27 port map(I0, I1, net_7);

  MUX2_0: MUX2 port map(net_F, net_7, I2, net_F7);
  MUX2_1: MUX2 port map(net_0, net_F7,  I3, O3);

-- output2: F1E1

  LUT21_0: LUT21 port map(I0, I1, net_1);
  LUT2E_0: LUT2E port map(I0, I1, net_E);

  MUX2_2: MUX2 port map(net_F, net_1, I2, net_F1);
  MUX2_3: MUX2 port map(net_E, net_1, I2, net_E1);
  MUX2_4: MUX2 port map(net_F1, net_E1, I3, O2);

-- output1: 3222

  LUT23_0: LUT23 port map(I0, I1, net_3);
  LUT22_0: LUT22 port map(I0, I1, net_2);

  MUX2_5: MUX2 port map(net_3, net_2, I2, net_32);
  MUX2_6: MUX2 port map(net_32, net_2, I3, O1);

-- output0: 5444

  LUT25_0: LUT25 port map(I0, I1, net_5);
  LUT24_0: LUT24 port map(I0, I1, net_4);

  MUX2_7: MUX2 port map(net_5, net_4, I2, net_54);
  MUX2_8: MUX2 port map(net_54, net_4, I3, O0);

end div_0_jv_BODY;

Guided part

• Create vhdl and Silicon compiler layout
• Simulate with LTspice for verification and delay
• LTspice run time and challenges
• Count number of transistors
• Attach pads and simulate with LTspice
• VHDL optimization options

Your task

• Optimize transistor count for your requested function
• Optimize transistor count for partial or complete add or multiply function

VHDL LUT Implementation

  MUX2_0: MUX2 port map(net_L3, net_L7, I2, Y2_0_0);
  MUX2_1: MUX2 port map(net_LE, net_L5, I2, Y2_0_1);
  MUX2_3: MUX2 port map(net_L4, net_L2, I2, Y2_0_2);
  MUX2_4: MUX2 port map(net_L5, net_L1, I2, Y2_0_3);
  MUX2_5: MUX2 port map(Y2_0_0, Y2_0_1, I3, Y2_1_0);
  MUX2_6: MUX2 port map(Y2_0_2, Y2_0_3, I3, Y2_1_1);
  MUX2_7: MUX2 port map(Y2_1_0, Y2_1_1, I4, Y2);  

-------------------- Cell LUT4_37E5{sch} --------------------
entity LUT4_37E5 is port(I0, I1, I2, I3: in BIT; Y: out BIT);
  end LUT4_37E5;

architecture LUT4_37E5_BODY of LUT4_37E5 is
  component LUT2E port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT23 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT25 port(I0, I1: in BIT; O: out BIT);
    end component;
  component LUT27 port(I0, I1: in BIT; O: out BIT);
    end component;
  component MUX4 port(I0, I1, I2, I3, I4, I5: in BIT; O: out BIT);
    end component;

  signal net_L5, net_L3, net_L7, net_LE: BIT;

begin
  LUT2E_0: LUT2E port map(I0, I1, net_LE);
  LUT23_0: LUT23 port map(I0, I1, net_L3);
  LUT25_0: LUT25 port map(I0, I1, net_L5);
  LUT27_0: LUT27 port map(I0, I1, net_L7);
  MUX4_0: MUX4 port map(net_L5, net_LE, net_L7, net_L3, I2, I3, Y);
end LUT4_37E5_BODY;

Verilog Counter Implementation

Counter used to test truth table or generate vectors

module  counter(clk, reset,max_tick,q); 
  #(parameter  N=8) 
    input  clk;  
	input reset; 
    output  max_tick; 
    output [N-1:0]  q; 
	
   //signal  declaration 
   reg  [N-1:0]  r_reg; 
   wire  [N-1:0]  r_next  ; 
//  body 
//  register 
   always  @(posedge clk,  posedge  reset) 
   if  (reset) 
     r_reg  <=  0;  //  {N{lb'O}} 
   else 
     r_reg  <=  r_next; 

//  next-state  logic 
   assign  r_next  =  r_reg  +  1; 
//  output  logic 
   assign  q  =  r_reg; 
   assign  max_tick  =  (r_reg==2**N-1)  ?  l'b1  :  l'b0; 
      //can  also  use  (r_reg=={N{l'bl))) 
endmodule

Verilog Truth Table Implementation

module tt4(clk,a,b); 
  input clk;
  input  [3:0] a;
  output [3:0] b;
  reg [3:0] newstate; 
  always @(posedge clk)   // clk sync truth table
  begin
   case (a)
    4'b0000 : newstate = 4'b0001;
    ..
    4'b1111 : newstate = 4'b0000;
    default : newstate = 4'b0000; // 
   endcase
  end 
  assign b = newstate;
endmodule
tt4 tt40(.clk(clk),.a(c),.b(c)); // makes counter 

module Counter4tt(clk,a,b);
  input clk;
  input  [3:0] a;
  output [3:0] b;
  reg [3:0] newstate;
  
  always @(posedge clk)   // truth table
  begin
   case (a)
    4'b0000 : newstate = 4'b0001;
    4'b0001 : newstate = 4'b0010;
    4'b0010 : newstate = 4'b0011;
    4'b0011 : newstate = 4'b0100;
    4'b0100 : newstate = 4'b0101;
    4'b0101 : newstate = 4'b0110;
    4'b0110 : newstate = 4'b0111;
    4'b0111 : newstate = 4'b1000;
    4'b1000 : newstate = 4'b1001;
    4'b1001 : newstate = 4'b1010;
    4'b1010 : newstate = 4'b1011;
    4'b1011 : newstate = 4'b1100;
    4'b1100 : newstate = 4'b1101;
    4'b1101 : newstate = 4'b1110;
    4'b1110 : newstate = 4'b1111;
    4'b1111 : newstate = 4'b0000;
    default : newstate = 4'b0000; // 
   endcase
  end 
  assign b = newstate;
endmodule

Optimization

• Optimize transistor count for your requested function
• Optimize transistor count for partial or complete add or multiply function

Deliverables