Interface Electronics03 Ideal ADC, DNL and INLProf. Dr. Jörg VollrathPrevious: 02 LTSPICE 
Länge: 01:06:27 
0:0:0 Start 0:1:22 ADC Converter metric 0:3:23 ADC transfer characteristic 0:4:40 First transition half LSB 0:6:35 2^n codes, 2^n1 transitions, 2^n2 steps 0:8:17 Transition table 0:9:15 Offset and gain error of ADC 0:11:39 Differential non linearity DNL 0:14:37 3bit, 8 codes, transitions 7, steps 6 0:17:16 DNL calculation 0:17:48 Sum DNL is zero 0:18:50 Integral non linearity INL 0:19:44 measurement of INL and DNL 0:21:32 Histogram test 0:26:30 INL sum of DNL 0:28:25 ADC Error simulator 0:29:11 Simulator ideal ADC ramp result 0:31:55 Introducing an distortion error 0:32:34 Transfer curve INl, DNL 0:35:29 Exam WS2010 Problem 1 0:36:50 LSB =(VMAXVMIN)/(2^n2) = (1.210.09)/14 V = 0.08 V 0:39:3 Math Notepad 0:39:45 Offset error 0.090.08/2 = 0.05 V 0:42:50 INL and DNL 0:44:13 INL(0100) = 0.525 0:46:0 DNL(0100) = 0.2 0:48:22 WS2011 Problem 1 Histogram 0:49:10 Don't use first and last occurences 0:50:0 navg = 15 0:50:59 DNL(1) = 0.2 0:52:0 DNL(2) = 0 0:53:0 INL(1) = 0.2 0:55:0 Resolution of histogram test 1/15 0:56:45 Simulator 0:57:27 INL, DNL simulation with noise 1:0:0 8bit simulation 1:2:50 small distortion 1:4:40 Sine input for histogram 1:7:40 Number of samples for sine histogram 1:10:43 Characterization system 1:14:15 WS2011 Problem 1 DAC 1:15:30 Excel data 1:16:10 First and last ideal voltage 1:16:30 LSB calculation 1:17:28 Ideal output voltages 1:18:24 LSB accuracy 1:19:37 DNL calculation 1:20:40 INL calculation 1:22:12 Plotting transfer curve 1:24:2 Plotting INL, DNL 
N: Number of Bits D_{0}..D_{N1}: Binary weighted data lines V_{in}: Positiv input voltage V_{max}: Maximum input voltage V_{FS}: Full scale voltage V_{ref}: Reference voltage Δ = LSB: minimum resolvable input For small N there is a significant difference LSB or Δ between V_{max}, V_{FS} and V_{ref}. In general \( V_{max} = V_{FS} = V_{ref}  LSB \) (Baker). For large N, LSB gets small and V_{max} = V_{FS} ≈ V_{ref}. 
Ideal analogtodigital converter An analog voltage or current is transfered into a digital output. Input range is positiv. Uniform, binary digital encoding 
Transition depends on measurement accuracy and step size. 
Vref = 1V N = 2 LSB = 0.25V Upper voltage limit (transition voltage) for a digital output code:

Offset Error, Gain Error Offset and gain error will be fixed during manufacturing. A trimmable amplifier is used. In this lecture first the LSB or Δ is calculated from the first and last points of the transfer curve. Then the offset is calculated for the first code or first transition voltage. Then static errors differential non linearity (DNL) and integral non linearity (INL) are calculated. 
Step size:
\( LSB = \frac{V(111)  V(000)}{2^{3}1} = 1 V \) The step size between 2 successive codes is normalized with LSB and calculated as DNL: \( DNL(n) = \frac{ V(n)  V(n1)  LSB}{LSB} \) Since the LSB is calculated using the first and last code: \( \sum DNL_i = 0 \) 
Step size: \( LSB = \frac{V(111)  V(000)}{2^{3}1} = 1 V \) The difference between real and ideal curve is normalized with LSB and calculated as INL: \( INL(n) = \frac{ V_{real}(n)  V_{ideal}(n)}{LSB} \) Since the INL is calculated using the first and last code: INL(000) = 0; INL(111) = 0; 
Apply input voltage ramp over time. Measure number of occurence of each output code. With a constant ramp slope (RS [V/s]) an ideal ADC with a sampling frequency fs and a step size of LSB gives: \( n(code) = \frac{LSB}{RS} \cdot f_s = n_{avg} \) Ideally n is constant for the input voltage range except for the first and last code. DNL can be calculated as: \( DNL(code) = \frac{n(code)  n_{avg}}{n_{avg}} \) INL is: \( INL(code) = \sum_{i=0}^{code} DNL(i) \) The accuracy for INL and DNL of this test is: \( \frac{1}{n_{avg}} \) 
It is difficult to build an analog linear ramp generator. A higher resolution DAC can be used. A sine input signal can be used. A high quality filter eliminates harmonics. Occurence will not be flat, but can be calculated in advance to normalize occurence to calculate INL and DNL. Occurence has a bathtub shape. At top and bottom highest occcurence can be seen, since the sine signal is flat. In the center low occurence can be seen due to the high slope of the sine signal. It is difficult to match the sine signal exactly to the input range of the ADC. 
How many samples M do you need of a sine input signal for a N Bit data converter? There will be more samples available at the top and bottom and less in the center. Signal: \( V(t) = 2^{N1} \cdot LSB \cdot sin \left( \omega t \right) \) Amplitude is: \( 2^{N1} \cdot LSB \) \( V'(t) = 2^{N1} \cdot LSB \cdot \omega \cdot cos \left( \omega t \right) \) Maximum change in signal after dt should be smaller than LSB: \( 2^{N1} \cdot LSB \cdot \omega \cdot dt \lt LSB \) with \( \omega = \frac{ 2 \pi}{M dt} \) \( M \gt 2 \cdot \pi \cdot 2^{N1} \approx 3 \cdot 2^N \) Having 16 times 2^{N} samples gives an accuracy for INL and DNL of \( \frac{3}{16} \approx 0.2 \). Having 8 times 2^{N} samples gives an accuracy for INL and DNL of \( \frac{3}{8} \approx 0.375 \). 
Error in sine signal estimateMake sure integer number of periods are used. Y = round((2^(n1)  0.5) + (2^(n1)  0.5) * sin(x*11/gr*2PI)) ; Y = round((2^(n1)  0.9) + ((2^(n1)  0.5) * sin(x*11/gr*2PI)) ; Y = round((2^(n1)  0.5) + ((2^(n1)  0.1) * sin(x*11/gr*2PI)) ; Bits: 5 Range: 0..31 1) Average shift:  0.4LSB 2) Amplitude increased: + 0.4LSB Fit a curve with minimum error. 