Review and Overview

Review:

• RC requirements
• DAC architectures
• R string DAC
• Interpolating DAC
  
• Parallel charge scaling DAC
• Equivalent sources
• Split array charge scaling DAC
• R2R DAC

Today:

• Realization of capacitances
• Example: R-string DAC
• Statistical resistor and capacitor variations: INL and DNL
• Switches, opamps and performance

Resistor string DA converter with mismatch

Version 4
SHEET 1 1884 680
WIRE -304 -464 -304 -480
WIRE -208 -416 -208 -448
WIRE -304 -368 -304 -384
WIRE -240 -368 -304 -368
WIRE -96 -368 -176 -368
WIRE -304 -352 -304 -368
WIRE -64 -352 -64 -448
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WIRE 32 -304 -32 -304
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WIRE -96 -256 -96 -304
WIRE -96 -256 -112 -256
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WIRE -96 416 -112 416
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FLAG -304 432 0
FLAG -304 -480 VREF
FLAG -208 -448 D0
FLAG -144 -448 D0b
FLAG -64 -448 D1
FLAG -16 -448 D1b
FLAG 64 -448 D2
FLAG 128 -448 D2b
FLAG 288 16 Vout
FLAG 240 160 0
SYMBOL Switch -144 416 M0
SYMATTR InstName X5
SYMBOL res -320 192 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL res -320 80 R0
SYMATTR InstName R2
SYMATTR Value 130
SYMBOL res -320 -32 R0
SYMATTR InstName R3
SYMATTR Value 100
SYMBOL res -320 -144 R0
SYMATTR InstName R4
SYMATTR Value 100
SYMBOL res -320 -256 R0
SYMATTR InstName R5
SYMATTR Value 90
SYMBOL res -320 -368 R0
SYMATTR InstName R6
SYMATTR Value 100
SYMBOL res -320 -480 R0
SYMATTR InstName R7
SYMATTR Value 100
SYMBOL res -320 304 R0
SYMATTR InstName R0
SYMATTR Value 80
SYMBOL Switch -208 304 M0
SYMATTR InstName X7
SYMBOL Switch -144 192 M0
SYMATTR InstName X8
SYMBOL Switch -208 80 M0
SYMATTR InstName X9
SYMBOL Switch -144 -32 M0
SYMATTR InstName X10
SYMBOL Switch -208 -144 M0
SYMATTR InstName X11
SYMBOL Switch -144 -256 M0
SYMATTR InstName X12
SYMBOL Switch -208 -368 M0
SYMATTR InstName X13
SYMBOL Switch -64 128 M0
SYMATTR InstName X14
SYMBOL Switch -64 -304 M0
SYMATTR InstName X15
SYMBOL Switch -16 -96 M0
SYMATTR InstName X16
SYMBOL Switch -16 352 M0
SYMATTR InstName X17
SYMBOL Switch 64 -192 M0
SYMATTR InstName X18
SYMBOL Switch 128 240 M0
SYMATTR InstName X19
SYMBOL cap 224 64 R0
SYMATTR InstName C1
SYMATTR Value 1n
TEXT -352 -584 Left 2 !.model CD4007N NMOS(LEVEL=1 KP=1123u VT0=0.5 LAMBDA=0.018)\n.model CD4007P PMOS(LEVEL=1 KP=1123u VT0=-0.5 LAMBDA=0.018)
TEXT 168 -504 Left 2 !.global VDD\n.include opamp.sub\nV4 d2b 0 PULSE(0 5 0 1n 1n 3999n 8000n)\nV1 d2 0 PULSE(5 0 0 1n 1n 3999n 8000n)
TEXT 232 -144 Left 2 !.tran 18000n
TEXT 160 -392 Left 2 !V2 d0b 0 PULSE(0 5 0 1n 1n 999n 2000n)\nV5 d0 0 PULSE(5 0 0n 1n 1n 999n 2000n)\nV6 d1 0 PULSE(5 0 0 1n 1n 1999n 4000n)\nV7 d1b 0 PULSE(0 5 0 1n 1n 1999n 4000n)\nVDD Vref 0 DC 4

Limits for DAC scaling

• DAC scaling limits
  • resolution, sample rate, power
• DAC architectures
  • R2R, C2C, ladder, unit element, current source
• Resolution
  • Noise, leakage, mismatch, voltage and temperature variation
• Sample rate
  • RC time constant

Mismatch and probability density

Real components have random variations Discrete resistors: 0.1%, 1%, 10% Integrated resistors: Manufacturing step variations Model for random variations: Probability density function Constant probability of variation. Mixing of probability functions gives a gaussian distribution

Gaussian distribution

Realization

Unit element mismatch and DNL

Only random error: Iref: reference current Rnom: nominal resistance $\Delta_i = I_{ref} \cdot R_i$ $DNL_{i} = \frac{\Delta_i - \Delta}{\Delta} = \frac{ R_i - R_{nom}}{R_{nom}} \approx \frac{dR}{R_i}$ $\sigma_{DNL} = \sigma_{R}$ 1% tolerance in resitance gives 1% = 0.01 DNL.

Unit element mismatch and INL: Theory

Only random error: E: Error at code x N: Number of maximum code A: Real output Ideal Variance A = x + E x x · σε2 B = N - x - E N - x (N - x) · σε2 Ratio: $r = \frac{x}{N}$ N = A + B E = A - x = A - r · N = A - r · (A + B) = (1 - r) · A - r · B Variance at code x: $\sigma_{INL}^2 = (1 - r)^2 \cdot \sigma_{A}^2 + r^2 \sigma_{B}^2$ $\sigma_{INL}^2 = (1 - r)^2 \cdot x \cdot \sigma_{\epsilon}^2 + r^2 \cdot (N-x) \cdot \sigma_{\epsilon}^2$ $\sigma_{INL}^2 = (x - 2 \cdot x \cdot r + x \cdot r^2 + r^2 \cdot N - x \cdot r^2) \cdot \sigma_{\epsilon}^2$ $\sigma_{INL}^2 = (x - 2 \cdot \frac{x^2}{N} + \frac{x^2}{N} ) \cdot \sigma_{\epsilon}^2$ $\sigma_{INL}^2 = (x - 2 \cdot \frac{x^2}{N} + \frac{x^2}{N} ) \cdot \sigma_{\epsilon}^2$ $\sigma_{INL}^2 = x \cdot \left( 1 - \frac{x}{N} \right) \cdot \sigma_{\epsilon}^2$

Unit element mismatch and INL

Only random error: $\sigma_{INL}^2(x) = x (1 - \frac{x}{N}) \cdot \sigma_{\epsilon}^2$ $\sigma_{INL}(x) = \sqrt{x (1 - \frac{x}{N})} \cdot \sigma_{\epsilon}$ Maximum: $\frac{\sigma_{INL}^2}{dx} = 0$ $1 - \frac{2 x}{N} = 0$ $x = \frac{N}{2}$ $\sigma_{INLmax} = \sqrt{\frac{N}{2} (1 - \frac{N}{2 \cdot N})} \cdot \sigma_{\epsilon}$ $\sigma_{INLmax} = \frac{1}{2} \sqrt{ N } \cdot \sigma_{\epsilon} = \frac{1}{2} \sqrt{ 2^{B} -1 } \cdot \sigma_{\epsilon}$

Example: N = 63

Binary weighted DAC DNL and INL

INL same as unit element INL. $\sigma_{INLmax} = \frac{1}{2} \sqrt{ 2^{B} -1 } \cdot \sigma_{\epsilon} \approx \frac{1}{2} \cdot 2^{\frac{B}{2}} \cdot \sigma_{\epsilon}$ Switching in the center: Half devices on, half minus one devices off DNL: Switching at center position: 011111..100000 $\sigma_{DNLmax}^2 = \left( 2^{B-1} - 1 \right) \cdot \sigma_{\epsilon}^2 + \left( 2^{B-1} \right) \cdot \sigma_{\epsilon}^2$ $\sigma_{DNLmax} \approx 2^{\frac{B}{2}} \cdot \sigma_{\epsilon} = 2 \sigma_{INLmax}$

Comparison INL and DNL: Binary weighted versus unit elements

Binary weighted topology R2R: $\sigma_{INLmax} \approx \frac{1}{2} \cdot 2^{\frac{B}{2}} \cdot \sigma_{\epsilon}$ DNL: $\sigma_{DNLmax} \approx 2^{\frac{B}{2}} \cdot \sigma_{\epsilon}$ $\sigma_{DNLmax} \approx 2 \sigma_{INLmax}$ B, 2B, 3B elements

Unit element topology R-string: $\sigma_{INLmax} \approx \frac{1}{2} \cdot 2^{\frac{B}{2}} \cdot \sigma_{\epsilon}$ DNL: $\sigma_{DNLmax} = \sigma_{\epsilon}$ 2B elements

Publication: Simulation of INL and DNL

Version 4
SHEET 1 1884 680
WIRE -304 -480 -304 -496
WIRE -112 -480 -112 -496
WIRE -304 -384 -304 -400
WIRE -240 -384 -304 -384
WIRE -112 -384 -112 -400
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FLAG -304 -496 VREF
FLAG -112 416 0
FLAG -112 -496 VREF
FLAG -240 64 VA3
FLAG -240 -48 VA4
FLAG -48 -48 VB4
FLAG -48 64 VB3
FLAG -240 176 VA2
FLAG -240 288 VA1
FLAG -240 400 VA0
FLAG -240 -160 VA5
FLAG -240 -272 VA6
FLAG -240 -384 VA7
FLAG -48 176 VB2
FLAG -48 288 VB1
FLAG -48 400 VB0
FLAG -48 -160 VB5
FLAG -48 -272 VB6
FLAG -48 -384 VB7
FLAG 96 -224 VD0
FLAG 96 -304 VD1
FLAG 96 -384 VD2
FLAG 272 -224 VCout
FLAG 96 32 V0
FLAG 96 -48 V0
FLAG 96 -128 V1
FLAG 272 32 VEout
FLAG 96 288 V1
FLAG 96 208 V1
FLAG 96 128 V0
FLAG 272 288 VFout
FLAG 416 -112 V0
FLAG 416 -192 V0
FLAG 416 -272 V0
FLAG 592 -112 VGout
FLAG 416 224 V1x
FLAG 416 144 V1x
FLAG 416 64 V1x
FLAG 592 224 VHout
FLAG 416 -368 V1x
FLAG 416 -16 V0
SYMBOL res -320 176 R0
SYMATTR InstName R1
SYMATTR Value 90
SYMBOL res -320 64 R0
SYMATTR InstName R2
SYMATTR Value 90
SYMBOL res -320 -48 R0
SYMATTR InstName R3
SYMATTR Value 110
SYMBOL res -320 -160 R0
SYMATTR InstName R4
SYMATTR Value 90
SYMBOL res -320 -272 R0
SYMATTR InstName R5
SYMATTR Value 90
SYMBOL res -320 -384 R0
SYMATTR InstName R6
SYMATTR Value 90
SYMBOL res -320 -496 R0
SYMATTR InstName R7
SYMATTR Value 90
SYMBOL res -320 288 R0
SYMATTR InstName R0
SYMATTR Value 90
SYMBOL res -128 176 R0
SYMATTR InstName R11
SYMATTR Value 90
SYMBOL res -128 64 R0
SYMATTR InstName R12
SYMATTR Value 90
SYMBOL res -128 -48 R0
SYMATTR InstName R13
SYMATTR Value 90
SYMBOL res -128 -160 R0
SYMATTR InstName R14
SYMATTR Value 110
SYMBOL res -128 -272 R0
SYMATTR InstName R15
SYMATTR Value 110
SYMBOL res -128 -384 R0
SYMATTR InstName R16
SYMATTR Value 110
SYMBOL res -128 -496 R0
SYMATTR InstName R17
SYMATTR Value 110
SYMBOL res -128 288 R0
SYMATTR InstName R10
SYMATTR Value 90
SYMBOL res 224 -400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RCD2
SYMATTR Value 100
SYMBOL res 224 -320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RCD1
SYMATTR Value 200
SYMBOL res 224 -240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RCD0
SYMATTR Value 400
SYMBOL res 224 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RED3
SYMATTR Value 90
SYMBOL res 224 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RED4
SYMATTR Value 220
SYMBOL res 224 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RED5
SYMATTR Value 440
SYMBOL res 224 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RFD1
SYMATTR Value 90
SYMBOL res 224 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RFD2
SYMATTR Value 220
SYMBOL res 224 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RFD6
SYMATTR Value 440
SYMBOL res 544 -288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RED1
SYMATTR Value 110
SYMBOL res 544 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RED2
SYMATTR Value 220
SYMBOL res 544 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RED6
SYMATTR Value 440
SYMBOL res 544 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RFD3
SYMATTR Value 110
SYMBOL res 544 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RFD4
SYMATTR Value 220
SYMBOL res 544 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RFD5
SYMATTR Value 440
SYMBOL res 544 -384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RED7
SYMATTR Value 45
SYMBOL res 544 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RFD7
SYMATTR Value 45
TEXT -728 -344 Left 2 !;tran 100n
TEXT -744 -272 Left 2 !VREF VREF 0 DC 0.8\nVD2 VD2 0 DC 0.7\nVD1 VD1 0 DC 0\nVD0 VD0 0 DC 0\nV1 V1 0 DC 0.7\nV0 V0 0 DC 0\nV1x V1x 0 DC 1.5
TEXT -736 -312 Left 2 !.op
TEXT -728 -536 Left 2 ;Unit Element A:  \nDNLmax = 2*dVR\nINLmax = dVR\nUnitElement B:\nDNLmax = dVR\nINLmax = (2^(NBit/2))/2 dVR
TEXT -752 48 Left 2 ;Binary Element E:\nDNLmax = 2 * INLmax\nINLmax = (2^(NBit/2))/2 dVR
TEXT -744 168 Left 2 !.save V(VA4) V(VA3)\n.save V(VB3) V(VB4) V(VB5)\n.save V(VCout) V(VEout) V(VFout)\n.save V(VHout) V(VGout)
TEXT -744 312 Left 2 ;10% Worst Case Error Investigation\nLSB = 0.1 V
TEXT 72 -488 Left 2 ;3 Bit Binary DAC
TEXT 368 -488 Left 2 ;4 Bit Binary DAC

Realization of resistors and capacitances

Process variables:

Undercutting Non uniformities Unit elements Ratio area to edge is constant. Common centroid design Systematic vertical and horizontal variations cancel out. Dummy elements

Capacitances

Resistors

Test and Calibration

Calibration

• Element trimming (laser fuse) at the end of wafer fabrication
• Inverse equation
• Lookup table
• Online background calibration

Test and strategy for calibration

• Identify topology: unit or binary weighted
• Unit elements
• Binary weighted elements
• Start in the center with biggest error

Laboratory and Calibration

• Measure DNL and INL
• For big steps in output voltage, DNL large, change capacitances.
  Jump at step 64, change capacitances at input D5 with a capacitance between D4 and D5.
• Negative steps or negative DNL create an equation
  if (code && 128) { code = code + x }
• Create new calibrated input code ramp and measure INL and DNL again.
• Create new calibrated input code for sine input signal and measure FFT, INL and DNL again.

DAC digital calibration example

Code 0 1 2 3 4 5 6 7 Vreal [V] 0 1.5 3 1.8 5 6 6.5 7 Videal [V] 0 1 2 3 4 5 6 7 INL 0 0.5 1 -1.2 1 1 0.5 0 DNL 0.5 0.5 -2.2 2.2 0 -0.5 -0.5 LSB = 1 V Slope Reversal Change Remove/reorder code 3,6 Adjust step size

DAC digital calibration example result

LSB =1 V Code range: 0..7 Lookup table, equation Code 0 1 1 3 2 4 5 7 CodeX 0 1 2 3 4 5 6 7 Vreal [V] 0 1.5 1.5 1.8 3 5 6 7 Videal [V] 0 1 2 3 4 5 6 7 INL 0 0.5 -0.5 -1.2 -1 0 0 0 DNL 0.5 -1 -0.7 0.2 1 0 0

DAC digital calibration example result

LSB =1.4 V Code range: 0..5 No power of 2! Lookup table, equation Code 0 1 2 3 4 5 6 7 CodeX 0 1 2 3 4 5 Vreal [V] 0 1.5 3 1.8 5 6 6.5 7 Videal [V] 0 1.4 2.8 4.2 5.6 7 INL 0 0.07 0.14 0.57 0.29 0 DNL 0.07 0.07 0.43 -0.29 -0.29

DAC digital calibration: 1 bit reduction

LSB =2.33 V Code range: 0..3 Lookup table, equation Code 0 1 2 3 4 5 6 7 CodeX 0 1 2 3 Vreal [V] 0 3 5 7 Videal [V] 0 2.33 4.67 7 INL 0 0.29 0.14 0 DNL 0.29 -0.14 -0.14

DAC digital calibration: 1 bit reduction

LSB =2 V Code range: 0..3 Lookup table, equation Code 0 1 2 3 4 5 6 7 CodeX 0 1 2 3 Vreal [V] 0 1.5 3 6 Videal [V] 0 2 4 6 INL 0 -0.25 -0.5 0 DNL -0.25 -0.25 0.5

DAC digital calibration summary

Next

References