07 DAC practical considerations

06 DAC errors

Video Lecture: DAC practical considerations

 Video is not visible, most likely your browser does not support HTML5 video Länge: 01:06:27 0:0:0 Interface Electronics 0:0:10 Ideal INL, DNL 0:0:42 DAC calibration example 0:3:3 Resistors and capacitances 0:5:35 Errors and resistance 0:6:53 DAC settling time Full scale, mid scale 0:11:29 DAC timing glitch 0:13:23 Sampling sine signal 0:15:8 DAC spectral measurement 0:18:20 DAC FFT with to many samples 0:24:17 One value per output code 0:25:3 DAC tool chain 0:26:4 DAC Evolution comparison 0:32:55 WS2012 Problem 4 0:38:11 Settling time 0:42:27 t > R C (B+1) ln(2) = 30 ns 0:46:0 Output voltage 0:48:51 Vout = (VD2/R3+VD1/R2+VD0/R1)Rout 0:54:34 Code = 001

Review and Overview

• Settling time
• Spurios signal coupling
• Timing error
• Reconstruction filter
• Spectral measurement
• Implementation examples

DAC settling time

 Data Conversion Handbook p.292 Full scale settling time: 000...111 Linear Technolgy (AN120f) Analog Devices MT-013 Mid scale settling time: 011..100 Analog Devices MT-013

DAC timing glitch

 Consider mid scale transition: 011..100 Full scale settling time: 000...111 Output depends on timing between LSB and MSB Ideal Late MSB Early MSB Application of a sample and hold.

Sampling a sine signal

 Sine signal (screen: 500x500 points) Looks smooth good Zoom: DAC signal generation Code has fixed sampling time and leads to steps > 1 LSB Oscilloscope has a fixed high sampling rate FFT only with filtered useful values
A sine function is generated with a x step size of 5.
The output looks like a low bit quantization despite using a very precise floating point number.
The y step size is very big for each step, but can vary a lot.

DAC spectral measurement

Just sampling in Excel gives a kind of quantization.

DAC spectral measurement

 Red dots ideal measurement One sample per output code after settling time Measurement with higher sample rate All samples, steps create harmonics Overshoot, undershoot? Measurement early during settling time FFT results

DAC distortion measurement

Sine signal and FFT
10 bit, 11 periods, 2048 points, 16 samples per point

Signal (11) 48 dB, total noise 31 dB (ideal simulation -10 dB)
Harmonics () 27 dB..12 dB
Noise floor peaks -26 dB, total noise -14 dB
You can not estimate levels looking at the graph with reasonable accuracy.
Numerical calculation is required.
10 log (N/2) = 30 dB
Excel:
x, column A: 0..2047 points
y, column B: = RUNDEN(511.5 + 511.5 * SIN(RUNDEN(A2 / 16;0) * 16/2048*11*2*PI());0)
Javascript:
Math.round(offset + amplitude * Math.sin( Math.round(i/nStep) * nStep / nPoints * nPeriods * 2 *Math.PI()))


Javascript FFT

DAC full system

 Reconstruction filters: Digital filter Band limit pre-emphasis to compensate for droop DAC Low pass filter switched capacitor and continuous time filter

DAC evolution comparison

 1986 2001 2008 Data Rate 80 MHz 1GS/s 12GS/s Resolution 8 bit (6+2) 10bit(5+5) 8bit(5+3) Technology 2 µm 0.35 µm 90nm Scaling factor 1 5.7 22 Supply voltage 5V 3V/1.9V 1.8V/1V Area 3.7mm2 0.35mm2 0.23mm2 Ratio expected/real 1/1 32/10 512/18 Power 145mW 110mW 190mW

Untrimmed segmented DACs:
T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC December 1986, pp. 983
A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” JSSC March 2001, pp. 315
Savoj, J, A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications , JSSC, 2008, pp. 1207 - 1216

Current copiers:
D. W. J. Groeneveld et al, “A Self-Calibration Technique for Monolithic High-Resolution D/A Converters,” JSSC December 1989, pp. 1517

Dynamic element matching:
R. J. van de Plassche, “Dynamic Element Matching for High-Accuracy Monolithic D/A Converters,” JSSC December 1976, pp. 795

Summary D/A converter

• D/A architecture
• Unit element – complexity proportional to 2B- excellent DNL
• Binary weighted- complexity proportional to B- poor DNL
• Segmented- unit element MSB(B1)+ binary weighted LSB(B2)
Complexity proportional ((2B1-1) + B2) -DNL good compromise
• Static performance
• Component matching
• Dynamic performance
• Time constants, Glitches
• DAC improvement techniques
• Symmetrical switching rather than sequential switching
• sample and hold
• Current source self calibration and digital assist
• Dynamic element matching
• Digital and analog reconstruction filter and error correction

DAC toolchain

 Digitalsignalgeneratorrampsine DAC:R-stringBinary R, CBinary: R2R, C2C Oscilloscope spectrum analyzer Theory Simulation High level Low level Circuit Measurement

1-bit oversampling DAC

• Low pass averaging of output
• Reduce bandwidth
• Improve resolution
Picture of a 1-bit oversampling DAC
Circuit and waveform

Next

08 Sampling and Jitter