2017 Laboratory 3: SPICE, DNL, INL, spectral analysis
Task:
Simulate a digital to analog converter.
Extract VFS, INL and DNL and do a spectral analysis.
Start LTSPICE.
Save all schematics of an DAC to your local working drive.
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Load the circuit 4Bit_C2C_DAC_Test into LTSPICE.
Make sure the ramp is active and simulation time is 16µs
checking the VIN statement and the .tran statement.
Start the simulation for a ramp: Simulate -> Run
- Include the schematic in your report
- Include the output waveform in your report.
Select the waveform window. Tools-> Copy bitmap to clipboard.
Paste the bitmap into your report.
- Include the SPICE netlist in your report.
View->SPICE netlist.
- Include the SPICE Error log in your report.
View->SPICE Error log.
Discuss the operation and the results.
The '.save V(vout)' command line makes only V(vout) available for plotting.
This is needed for further data processing.
You can comment the line out using a '*' or a ';'.
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Version 4
SHEET 1 1884 680
WIRE 160 -96 112 -96
WIRE 256 -96 224 -96
WIRE 288 -96 256 -96
WIRE 368 -96 352 -96
WIRE 400 -96 368 -96
WIRE 480 -96 464 -96
WIRE 512 -96 480 -96
WIRE 592 -96 576 -96
WIRE 688 -96 592 -96
WIRE 736 -96 688 -96
WIRE 112 -80 112 -96
WIRE 256 -80 256 -96
WIRE 368 -80 368 -96
WIRE 480 -80 480 -96
WIRE 592 -80 592 -96
WIRE 816 -80 800 -80
WIRE 864 -80 816 -80
WIRE 736 -64 720 -64
WIRE 720 -32 720 -64
WIRE 816 -32 816 -80
WIRE 816 -32 720 -32
WIRE 0 -16 -48 -16
WIRE 256 0 256 -16
WIRE 368 0 368 -16
WIRE 480 0 480 -16
WIRE 592 0 592 -16
WIRE -176 16 -208 16
WIRE 0 16 -48 16
WIRE -176 48 -208 48
WIRE 0 48 -48 48
WIRE -176 80 -208 80
WIRE 0 80 -48 80
WIRE 0 112 -48 112
WIRE 240 160 240 144
WIRE 352 160 352 144
WIRE 352 160 240 160
WIRE 464 160 464 144
WIRE 464 160 352 160
WIRE 576 160 576 144
WIRE 576 160 464 160
WIRE 720 160 576 160
WIRE 112 176 112 -16
WIRE 272 176 272 144
WIRE 272 176 112 176
WIRE 384 176 384 144
WIRE 384 176 272 176
WIRE 496 176 496 144
WIRE 496 176 384 176
WIRE 608 176 608 144
WIRE 608 176 496 176
WIRE 720 176 608 176
WIRE 224 192 224 112
WIRE 336 192 336 112
WIRE 448 192 448 112
WIRE 560 192 560 112
WIRE 720 192 720 176
FLAG 864 -80 Vout
IOPIN 864 -80 Out
FLAG 720 160 Vref
IOPIN 720 160 In
FLAG 720 192 0
FLAG 448 192 D2
IOPIN 448 192 In
FLAG 336 192 D1
IOPIN 336 192 In
FLAG 224 192 D0
IOPIN 224 192 In
FLAG 688 -96 Vint
FLAG 560 192 D3
IOPIN 560 192 In
FLAG -208 16 CLK
FLAG -208 48 Vin
FLAG -208 80 VDD
FLAG 0 -16 D0
FLAG 0 16 D1
FLAG 0 48 D2
FLAG 0 80 D3
FLAG 0 112 RES
SYMBOL cap 464 -80 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL cap 352 -80 R0
SYMATTR InstName C2
SYMATTR Value 10p
SYMBOL cap 240 -80 R0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL cap 464 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 10p
SYMBOL cap 576 -80 R0
SYMATTR InstName C5
SYMATTR Value 10p
SYMBOL cap 96 -80 R0
SYMATTR InstName C6
SYMATTR Value 10p
SYMBOL cap 224 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 10p
SYMBOL cap 352 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C8
SYMATTR Value 10p
SYMBOL cap 576 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C9
SYMATTR Value 10p
SYMBOL cap 240 0 R0
SYMATTR InstName C10
SYMATTR Value 10p
SYMBOL cap 352 0 R0
SYMATTR InstName C11
SYMATTR Value 10p
SYMBOL cap 464 0 R0
SYMATTR InstName C12
SYMATTR Value 10p
SYMBOL cap 576 0 R0
SYMATTR InstName C13
SYMATTR Value 10p
SYMBOL 4Bit_ADC_pipe -112 48 R0
SYMATTR InstName X4
SYMBOL Switch4 256 112 R270
SYMATTR InstName X1
SYMBOL Switch4 368 112 R270
SYMATTR InstName X2
SYMBOL Switch4 480 112 R270
SYMATTR InstName X3
SYMBOL Switch4 592 112 R270
SYMATTR InstName X5
SYMBOL Opamp2 768 -80 R0
SYMATTR InstName X6
SYMATTR SpiceLine Aol=1000k GBW=1000k
TEXT -184 -280 Left 2 !.global VDD\n.include cmosedu_models.txt\nVIN VIN 0 PULSE(0 1 0 16u 16u 0n 32u)\n*VIN VIN 0 SINE(0.5 0.5 74218.75 0 0 0)\nVCLK CLK 0 PULSE(0 5 0 1n 1n 1n 1u)
TEXT 280 -160 Left 2 !.tran 16u
TEXT 280 -280 Left 2 !Vref Vref 0 DC 1\nVDD VDD 0 DC 1
TEXT 712 24 Left 2 !.save V(vout)
TEXT 272 -224 Left 2 ;ramp needs 16us simulation time\nsine needs 256us simulation time
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- Use the tool ReadRawFile_ADC.html for reading one column of LTSPICE data.
'.save V(vout)' has to be active.
The output values will be scaled with the range into positiv integer values.
Select a convenient output range for simulation (integer * #steps = integer * (2N-1)).
The timestep will sample data in the LTSPICE raw output file at 1/2*tS, 3/2*tS, 5/2*tS ..
Select a timestep matching the simulation.
Select the option for ramp INL, DNL analysis.
Select your LTSPICE raw output file.
- Report minimum and maximum value, INL and DNL and discuss the results.
- Change the simulation for a sinewave:
Simulation time 256µs to get 256 values.
Activate the input sine signal.
Redo the simulation.
What happens for different starting values 'Phi' of the voltage source?
Use the tool ReadRawFile_ADC.html with the option
'Map to positive integer' for reading one column of LTSPICE data.
Use the tool FFT_Javascript_2017_Calibration.html
for doing a FFT and a histogramm test.
Paste the integer data into the 'Input Data' field, do read 'Integer Data' and 'Generate Charts'.
Document your results and discuss signal to noise behaviour.
- Redo INL, DNL and signal to noise ratio calculations with errors in capacitances:
- All capacitances 10pF except for C5 = 15 pF and C13 = 15 pF.
- All capacitances 10pF except for C9 = 15 pF.
- All capacitances 10pF except for C2 = 15 pF and C11 = 15 pF.
Report and discuss the results.
Report
Make a report as a pdf document from a Word document or a web page.
You can use the source code of this web page or there is a
web page template available here.
Additional files are here as an zip file (39 MB).
Send a ziped group directory with your data containing also a printout of the webpage in a pdf
file to joerg.vollrath@fh-kempten.de.
You can use the freeware program PDF Creator for generating the pdf file.
The directory should be named with the year, group number and last name
<year>_Group<###>_<Last_name>
Example: 2017_Group01_Vollrath
In this directory put the html and pdf file.
The file name should contain the date, the laboratory and your last names.
<year>_<month>_<Date>_InEl_Lab02_<Last_name1>_<Last_Name2>.pdf
Example: 2017_10_24_InEl_Lab03_Vollrath_studentx.html
Example: 2017_10_24_InEl_Lab03_Vollrath_studentx.pdf

Grading:
Each question should be answered. The answer should be correct/make sense. There should be some
text discussing the work strategy, obstacles and results.
The submission date will be graded. Submission should happen until 22.11.2017.
Late submission will be downgraded.
A nice document format and correct use of English language and spelling is graded.
Version 4
SymbolType BLOCK
LINE Normal -32 32 -32 -31
LINE Normal 32 0 -32 32
LINE Normal -33 -32 32 0
LINE Normal -11 -16 -25 -16
LINE Normal -19 -10 -19 -21
LINE Normal -9 16 -23 16
WINDOW 0 0 -40 Bottom 2
PIN -32 16 NONE 8
PINATTR PinName M
PINATTR SpiceOrder 1
PIN -32 -16 NONE 8
PINATTR PinName P
PINATTR SpiceOrder 2
PIN 32 0 NONE 8
PINATTR PinName Y
PINATTR SpiceOrder 3
Version 4
SymbolType BLOCK
LINE Normal 49 1 31 1
LINE Normal 31 1 -16 -4
LINE Normal 0 -2 -8 -16
LINE Normal 8 -15 0 -2
LINE Normal -32 -16 -16 -16
LINE Normal -32 16 -16 16
LINE Normal 0 -2 0 -32
PIN 0 -32 NONE 8
PINATTR PinName ctrl
PINATTR SpiceOrder 1
PIN -32 -16 NONE 8
PINATTR PinName in1
PINATTR SpiceOrder 2
PIN -32 16 NONE 8
PINATTR PinName in2
PINATTR SpiceOrder 3
PIN 48 0 NONE 8
PINATTR PinName out
PINATTR SpiceOrder 4
Version 4
SymbolType BLOCK
RECTANGLE Normal -64 -88 64 88
WINDOW 0 0 -88 Bottom 2
PIN -64 -32 LEFT 8
PINATTR PinName CLK
PINATTR SpiceOrder 1
PIN -64 0 LEFT 8
PINATTR PinName In1
PINATTR SpiceOrder 2
PIN -64 32 LEFT 8
PINATTR PinName VDD
PINATTR SpiceOrder 3
PIN 64 -64 RIGHT 8
PINATTR PinName D0
PINATTR SpiceOrder 4
PIN 64 -32 RIGHT 8
PINATTR PinName D1
PINATTR SpiceOrder 5
PIN 64 0 RIGHT 8
PINATTR PinName D2
PINATTR SpiceOrder 6
PIN 64 32 RIGHT 8
PINATTR PinName D3
PINATTR SpiceOrder 7
PIN 64 64 RIGHT 8
PINATTR PinName Out
PINATTR SpiceOrder 8