Hochschule Kempten      
Fakultät Elektrotechnik      
Interface Electronics       Fachgebiet Elektronik, Prof. Vollrath      

Interface Electronics

Lab 04 Analyze, Simulation and Calibration of a 8bit R2R-DAC

***742R, ***136H


Building a 8 bit DAC

  • Connect two 4_bit R2R DAC to make 8-bit DAC in LTspice as showns in schamatic
  • Measure provided resistance and replace resistance value with measured one
  • Connect resistor in breadbord in form of R2R DAC as showm in figure 1
  • Creat symbol for 8-bit ADC with two cascaeded 4-bit ADC as schamatic 1
figure 1 schamatic 1

Simulation of DAC with ramp test

  • Input ramp for ADC is shown in figure 1
  • Extract the simulated values with Read Raw File with start time 0, end time 655.36u
  • End time is total time devided by number of code(256).
  • Calculate INL, DNL using tool ReadOsci.html and paste the extracted values from LTSPICE into the input field.
  • DNL found in acceptable range from -0.55 till 0.05
  • INL found -0.25 till 0.25 as shown in figure 2
  • This error is due to deviation of in resisyance value from ideal.
                  figure 1 figure 2

Simulation of DAC with sine test

  • Provides sine signal to ADC
  • Extract the simulated values with Read Raw File
  • Calculate FFT, INL, DNL with FFT webpage
  • Paste the extracted values from LTSPICE into the input field.
  • INL and DNL are are as shown in figure 1 and histrogram is also shownin figure 2
  • spectral values can be sheen in from figure 3
  • Ratio of rms signal to rms noise is shown in table 1
  • Signal: 36.11 dB at 11 Hz, Noise peak: -18.59 dB Total Noise: -11 dB SNR = 1.76 dB + 6.02*8 dB + 10log10( 256*2^8/ 2 )=95.07 dB
figure 1 figure 2 figure 3 table 1

Measuring the real DAC

Measure Vout with difference input frequency

  • Select D0 - D7 in "Waveforms as Bus
  • Select binary counter to get a ramp output
  • Select frequency of 10Mhz (fig 1), 1Mhz (fig 2), 100kHz (fig 3), 10Hz (fig 4)
  • Select Trigger to CH1
  • Connect CH2 to output and CH1 to MSB
  • Adjust the time Base to get only one Ramp on screen
  • Interesting is the falling slope
  • For frequencies above 10kHz you can easily see a round edge
    -> settling time is to large for this input frequencies
figure 1 figure 2 figure 3 figure 4

Measuring Settling time part 1

  • For Settime from 0-255
  • Select D0 - D7 in "Waveforms as Bus
  • Select "clock" to toggle the input from 0 - 255
  • Select clock to 2kHz (it was slightly round at 10kHz you see task before)
  • Connect Scope CH1 to MSB, CH2 to DAC-Output
  • Select Trigger to CH1 rising edge (fig 1) and falling edge (fig 2)
  • Adjust the time base to get only the transient on screen
  • Measure time differnce from 0 until signal is fully rised: ~25us
  • Measure time differnce from 255 until signal is dropped: ~25us
  • Unfortunate we not zoomed in so well
    -> so we may see not full settling
figure 1 figure 2

Measuring Settling time part 2

  • For Settime from 127-128 (1LSB)
  • Select D0 - D6 in "Waveforms as Bus and D7 as own signal
  • Set phaseshift between D7 and Bus to 180 degree
  • Zoom in CH2 to measeure rise time (use DC coupling)
  • Measure time differnce until signal is fully rised: 4us
  • Measure time differnce until signal is dropped: 4us
  • We see the maximum frequency without loosing accuracy is 1/Tset = 1/25us= 40kHz
  • We 0-255 value because step at the end of ramp will be from 255 - 0
  • When zooming in with ReadOsci tool we saw that settling time
    we measured was to low (code 00000000 not reached)
  • We recognized max frequ. ~2kHz
figure 1

Export data with ReadOsci tool

  • Set Number of Data to 8192 (this is the fixed number of sample points of the explorer board)
  • Set averaging to 4 to reduce noise influence
  • Set number of values to 256 according to the 8bit DAC
  • Selecting the ramp as follows:
  • Select DNL/INL start to the sample number where the ramp starts
  • Check if you are right with the zoom function
  • Set DNL/INL to (#Samp_end-#Samp_start)/256
  • Check if you are right with the zoom function e.g. checking upper limit in fig. 2
  • The samples should be in the middle od each step
  • Select map to pos. integer
  • Process oscilloscope data
figure 1 figure 2

Measuring ramp test

  • Select D0 - D7 in "Waveforms as Bus
  • Select Binary Counter to get a ramp as DAC output
  • Set frequency to 2kHz (frequency should be smaller than max. settl. time)
  • In the figure 1 we selected 10kHz
  • So we may not reach the code 00000000
  • Select Trigger to CH2
  • Adjust the time base to get only one ramp on the screen
    so you have maximum number of samples per ramp
  • Export the Data to a .cvs file
  • Replace "," with "."
  • Copy the data to ReadOsci tool
  • You can see in the scope menupoint "Data" at which sample number the ramp starts/ends
figure 1

Calculate INL/DNL

  • Select now Ramp INL, DNL
  • Process oscilloscope data so that DNL will be ploted
  • The tool will calc.
  • You see DNL are mostly pos. -> INL is increasing until ~127
  • Then DNL is neg. and INL drops largely
  • We already saw the jump at D7 in the simulation result
  • -> The value of R15 (D7) is to high (because output voltage to low)
  • additional most other voltages are a little bit to high
    -> INL rising from 0 - 127


  • Change R15 with R2 to compensate the mentioned problem
  • Reduce the Ramp measurement, export and INL/DNL calc.
  • We see now the peak of the DNL is reduced from 800m to 300m
  • (due to the zoomed scale on y-axis it looks worth but it isn't)
  • But DNL is now a little bit to low
  • INL/DNL should not exeed 0.5 to loose no bit
  • So we need further optimization
  • Further Optimazation

  • Change R1 with R3 to reduce the nagative INL
  • We need "more" positive DNL
  • R1 is smaller than R3 -> D2 voltage will rise little bit
  • Redue the Ramp measurement, export and INL/DNL calc.
  • We see now the peak INL and DNL is below 0.5LSB
  • So we lose no bit
  • Optimazation is done now
  • Sine Measurement

  • To generate a sinusoidal output with the DAC
    we need a certain input pattern. Available here
  • Load the pattern in the generator sowftware
  • We selected 2kHz so that settling time doesn't cause problems
  • It is a 10bit signal, so select bit_2 to bit_9 for the 8bit DAC
  • Choose the Osci timebase that all 43 periods are displayed
  • Because we have an odd number of samples we catch all DAC
    stairs at diffrent periods
  • Upload the exported Data to ReadOsci
  • We choose averaging 4 samples to smooth errors caused by noise
  • The INL/DNL Start is selected that the samples are in the middle of each step
  • FFT Analysis

  • We copy the mapped to integer data to the FFT page
  • Unfortunate we see that the INL/DNL is worse compared with the ramp test
  • We expected very close values like an INL/DNL <0.5
  • FFT wrong selection of Data

  • If your exported data covers not only full periods
  • You get some harmonics which actually are not there (see figure)
  • So ENOB are worse than in reality
  • You can minimize this by using a window function
  • But sampling full periods is the best and easiest way
  • DAC Calibration Ramp1

  • Now we want to calibrate the DAC by software
  • We now select the best codes for DAC by software
  • We apply again a ramp to the DAC
  • We use now a ramp which is flat at the start and the end
  • It is easier to select the right Data with ReadOsci
  • The Data for the Wave Board are generated with this tool
  • Select 8 bit and Ramp EE vector and press "Generate default calibration"
  • Save the generated Data in an .csv file and import it in WaveForms
  • There is an additional sync_bit (fig. 2), so add bit 9 to the Output-BUS
  • Connect CH1 of the scope to bit_9 signal and trigger on that CH1
  • The displayed CH2 is now stable
  • figure 1 figure 2

    DAC Calibration Ramp2

  • Now export the Data to the ReadOsci
  • Select the Data as discribed before
  • Now select "Calibration ramp data:Integer"
  • You get now new 256 numbers of codes
  • But there are now some codes missing
  • 215 codes of 256 are used
  • We were a bit supprised that so many codes were missing
    despite our uncalibrated ramp wasn't so bad
  • The new ramp Data for the Wave Board are generated with this tool
  • Select 8 bit and Ramp EE vector and insert your calibrated codes"
  • Redue the measurement like before
  • Unfortunate the INL/DNL increased after calibration
  • We are pretty shure that we selected the data right
    and the large DNL at zero is caused by calibration (not wrong data selection)
  • Sine with uncalibrated pattern

  • First we apply again a digital pattern for a output sine
  • You can generate the pattern with this tool
  • Export the Data
  • Map the Data to pos. integers
  • Using the FFT tool
  • In the INL/DNL chart we read a max. value ~1.6
  • We expected a max. below 0.5 due to the calibration
  • In the table we can read SNR 84.27-35.15 = 49.12dB
  • So we can calculate the ENOB:
  • 49.12dB -1.76dB / 6.02 dB = 7.87 (bit)
  • This is pretty close to 8bit
  • Due to ramp test (below 0.5LSB) we expected 8 bits
  • Calc. Signal to distortion ration:
  • SDR = SigPower - DistPower
  • SDR = 84.3dB - 20.9dB = 63.4dB
  • Sine with calibrated pattern

  • Now we apply again a digital pattern for a output sine
  • You can generate the pattern with this tool
  • Additionally you insert the Calibration values from ramp test
  • Export the Data and recalculate the FFT
  • Unfortunate the INL/DNL is worse in comparision with no calibration
  • In the SNR table you see pretty similar data
  • So calibration brought no improvement
  • The ENOB still ~7.87 bit
  • SDR slightly decreased to 62.8dB
  • Challenges of the Lab

  • Getting familliar with the JS-Tools takes a lot of time and is not so easy
  • The videos helped a lot
  • Sometimes loose connection causes unexpected worse results
  • We were confused when "optimazation" brings no improvement
  • The "new" ramp with a plato makes it easier to select bottom/top values
    we had some problems to select the lower and upper limits due to noise on LSB