Interface ElectronicsLab01..03 Web report, LTSPICE and data convertersGroupE00 ***700, C |
To the following circuit, different analysis were carried out.
The result of the simulations is as follows:
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Version 4 SHEET 1 880 680 WIRE 160 0 48 0 WIRE 240 0 160 0 WIRE 240 32 240 0 WIRE 48 96 48 0 WIRE 240 128 240 112 WIRE 336 128 240 128 WIRE 240 144 240 128 WIRE 48 240 48 176 WIRE 240 240 240 208 WIRE 240 240 48 240 WIRE 240 272 240 240 FLAG 240 272 0 FLAG 160 0 VDD FLAG 336 128 Vout SYMBOL voltage 48 80 R0 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value2 AC 1 SYMATTR InstName V1 SYMATTR Value SINE(4 1 10k) SYMBOL res 224 16 R0 SYMATTR InstName R1 SYMATTR Value 100k SYMBOL cap 224 144 R0 SYMATTR InstName C1 SYMATTR Value 50n TEXT 48 272 Left 2 !;op TEXT 48 312 Left 2 !;tran 0.2m TEXT 48 352 Left 2 !.ac dec 10 1 10k |
The result of this analysis is table of values, which correspond to the values of DC steady-state analysis, treating the capacitances as an open circuit. The values obtained are reasonable, in order that for the DC analysis, the voltage should be the same at the output. A value for the current was obtained, however it is too small that is practically considered to be zero. |
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The result of this analysis is a graphic in which the behaviour of the circuit could be observed in the time domain. As the name of the analysis, with this option the transient behaviour of the circuir could be observed. As expected for the circuit, as the input is a sinusoidal wave, the output has the same property. Taking into account that this circuit is a low-pass filter, is reasonable that to a frequency of 10kHz the output is attenuated. This is beacuse the bandwidth of the filter is defined as: F_c = \frac{1}{2 \pi {R} {C}} = 31.8 {Hz} which is a value much lower than 10 kHz |
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This analysis allow us to make the small signal analysis over the DC operating point. As inputs, the selection of the limits to the frequency sweep are available. In the result, it can be seen that the output is the bode plot for the circuit at the band defined in the analysis. For the specific circuit, the frequency edge is almost 32 Hz by the formula. It can be seen that this number is nearly the value of -3dB magnitude |
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Following the instructions to build the schematic shown in the image, simulations were held from a sine and ramp input, in order to obtain data and measure the DNL and INL values |
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The figure shows that the converter is following the form of the sine wave, but with fixed steps as it is an output based on fixed values. As the converter is 4 bit, the steps are 16. It can also be seen that the maximum output voltage is not the reference voltage, instead a voltage below 950 mV. The LSB can be calculated easily with the following formula: LSB = \frac{V_ref}{2^{N}} = 1/16 = 62.5{mV} and therefore, the maximum output voltage is: V_{out,max} = {LSB} \times ({2^{N}-1}) = 937{mV} \times 15 = 937{mV} |
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The figure shows that the converter is following the form of the ramp wave, but with fixed steps as it is an output based on fixed values. As the converter is 4 bit, the steps are 16. The calculations are also valid for this signal: LSB = \frac{V_ref}{2^{N}} = 1/16 = 62.5{mV} and therefore, the maximum output voltage is: V_{out,max} = {LSB} \times ({2^{N}-1}) = 937{mV} \times 15 = 937{mV} |
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The figure shows the graphics of ADC - DNL and INL from the data of the simulation. That are the typical curves for DNL and INL for a sine wave using the histogram test. |
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The figure shows the graphics of DAC - DNL and INL from the data of the simulation. Here there is no error between the real and expected values, and therefore the DNL and INL are zero for all codes. |
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The figure shows the graphics of ADC - DNL and INL from the data of the simulation. As the input is a ramp wave, and all the codes in the histogram have the same amount of samples, there is no error, and therefore no DNL and INL |
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The figure shows the FFT of the sine wave. There can be seen a peak at frequency 11. There are also some components of high frequency, but most of it could be considered the average noise magnitude. |
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The figure shows the magnitude of the sine wave FFT components. The principal component is located at frequency 11, and from there there is a margin of 25dB. |
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The following schematic shows the implementes R2R architecture. of the simulation. The values of resistances are not the same, and therefore will be a change in the iutput characteristic curve. |
Version 4 SHEET 1 880 1532 WIRE 560 -288 480 -288 WIRE 80 -192 16 -192 WIRE 112 -192 80 -192 WIRE 128 -192 112 -192 WIRE 224 -192 208 -192 WIRE 240 -192 224 -192 WIRE 336 -192 320 -192 WIRE 352 -192 336 -192 WIRE 448 -192 432 -192 WIRE 480 -192 480 -288 WIRE 480 -192 448 -192 WIRE 512 -192 480 -192 WIRE 624 -192 592 -192 WIRE 624 -176 624 -192 WIRE 112 -160 112 -192 WIRE 224 -160 224 -192 WIRE 336 -160 336 -192 WIRE 448 -160 448 -192 WIRE 16 -144 16 -192 WIRE 624 -80 624 -112 WIRE 112 -48 112 -80 WIRE 224 -48 224 -80 WIRE 336 -48 336 -80 WIRE 448 -48 448 -80 WIRE 16 -16 16 -64 WIRE 512 96 480 96 WIRE 288 128 256 128 WIRE 512 128 480 128 WIRE 128 160 80 160 WIRE 288 160 256 160 WIRE 512 160 480 160 WIRE 128 192 80 192 WIRE 288 192 256 192 WIRE 512 192 480 192 WIRE 688 192 640 192 WIRE 128 224 80 224 WIRE 288 224 256 224 WIRE 512 224 480 224 WIRE 288 256 256 256 WIRE 512 256 368 256 WIRE 368 272 368 256 WIRE 512 288 464 288 FLAG 80 160 CLK IOPIN 80 160 In FLAG 80 224 VDD IOPIN 80 224 In FLAG 368 272 0 FLAG 80 192 in1 IOPIN 80 192 In FLAG 288 256 RES1 FLAG 288 224 D3 FLAG 288 192 D2 FLAG 288 160 D1 FLAG 288 128 D0 FLAG 480 96 CLK FLAG 464 288 VDD FLAG 480 128 D0 FLAG 480 160 D1 FLAG 480 192 D2 FLAG 480 224 D3 FLAG 688 192 Voutx IOPIN 688 192 Out FLAG 16 -16 0 FLAG 112 -48 D0 IOPIN 112 -48 In FLAG 624 -80 0 FLAG 624 -192 Voutfx FLAG 224 -48 D1 IOPIN 224 -48 In FLAG 336 -48 D2 IOPIN 336 -48 In FLAG 448 -48 D3 IOPIN 448 -48 In FLAG 560 -288 Vout IOPIN 560 -288 Out FLAG 80 -192 V0L FLAG 224 -192 V1L FLAG 336 -192 V2L SYMBOL 4Bit_DAC_pipe 576 192 R0 SYMATTR InstName X2 SYMBOL 4Bit_ADC_pipe 192 192 R0 SYMATTR InstName X4 SYMBOL res 0 -160 R0 SYMATTR InstName R1 SYMATTR Value 2k SYMBOL res 96 -176 R0 SYMATTR InstName R2 SYMATTR Value 2k SYMBOL res 112 -176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res 608 -208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 10k SYMBOL cap 608 -176 R0 SYMATTR InstName C1 SYMATTR Value 1p SYMBOL res 208 -176 R0 SYMATTR InstName R5 SYMATTR Value 2k SYMBOL res 224 -176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R6 SYMATTR Value 1.7k SYMBOL res 320 -176 R0 SYMATTR InstName R7 SYMATTR Value 2.5k SYMBOL res 448 -176 M270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL res 432 -176 R0 SYMATTR InstName R9 SYMATTR Value 1.5k TEXT -8 312 Left 2 !VDD VDD 0 DC 1\nVCLK CLK 0 PULSE(0 1 0 1p 1p 5n 10n) TEXT 480 344 Left 2 !.tran 0 655.36u 0 1n TEXT 480 376 Left 2 !.options plotwinsize=0 TEXT 440 408 Left 2 !*.save V(vout) V(in1) V(clk) V(d*)\n.save V(vout) TEXT -8 368 Left 2 !V2 in1 0 SINE(0.5 0.5 16784.66796875) TEXT -24 488 Left 2 ;V1 in1 0 PULSE(0 1 0 655.36u 655.36u 0 1310.72u) |
The following DNL and INL graphics is the response to the ramp wave. As expected, there is a change in the output characteristic, as the output values are not longer equilibrated to LSB steps, due to the change in the resistor values divisor are not set to the same ratio. |
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The following DNL and INL graphics is the response to the sine wave. The DNL has almost the same behaviour as in the ideal case. But there are to peaks for 2 codes in the middle. The INL is icreasing as the DNL has no negative values. |
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The following FFT graphics is the response to the sine wave. In real time, it can be seen that codes for middle values is nearly inexistent, but for the non-linear part of the sine, there are codes which are close to each other. The FFT of the signal looks very similar to the ideal one.Exists the same peak frequency, but the harmonics are more distinguishable. |
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The figure shows the magnitude of the signal and the harmonics. According to this data, now the SNR is about 16.33 dB, which is considerably less than the ideal case. However, there is no lost of bits in this case |
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Version 4 SymbolType BLOCK RECTANGLE Normal -64 -120 64 120 WINDOW 0 0 -120 Bottom 2 PIN -64 -96 LEFT 8 PINATTR PinName CLK PINATTR SpiceOrder 1 PIN -64 -64 LEFT 8 PINATTR PinName D0 PINATTR SpiceOrder 2 PIN -64 -32 LEFT 8 PINATTR PinName D1 PINATTR SpiceOrder 3 PIN -64 0 LEFT 8 PINATTR PinName D2 PINATTR SpiceOrder 4 PIN -64 32 LEFT 8 PINATTR PinName D3 PINATTR SpiceOrder 5 PIN -64 64 LEFT 8 PINATTR PinName In1 PINATTR SpiceOrder 6 PIN -64 96 LEFT 8 PINATTR PinName VDD PINATTR SpiceOrder 7 PIN 64 0 RIGHT 8 PINATTR PinName Out PINATTR SpiceOrder 8
Version 4 SymbolType BLOCK RECTANGLE Normal -64 -88 64 88 WINDOW 0 0 -88 Bottom 2 PIN -64 -32 LEFT 8 PINATTR PinName CLK PINATTR SpiceOrder 1 PIN -64 0 LEFT 8 PINATTR PinName In1 PINATTR SpiceOrder 2 PIN -64 32 LEFT 8 PINATTR PinName VDD PINATTR SpiceOrder 3 PIN 64 -64 RIGHT 8 PINATTR PinName D0 PINATTR SpiceOrder 4 PIN 64 -32 RIGHT 8 PINATTR PinName D1 PINATTR SpiceOrder 5 PIN 64 0 RIGHT 8 PINATTR PinName D2 PINATTR SpiceOrder 6 PIN 64 32 RIGHT 8 PINATTR PinName D3 PINATTR SpiceOrder 7 PIN 64 64 RIGHT 8 PINATTR PinName Out PINATTR SpiceOrder 8