Hochschule Kempten      
Fakult├Ąt Elektrotechnik      
Interface Electronics       Fachgebiet Elektronik, Prof. Vollrath      

Interface Electronics

Laboratory 03: ADC DAC analysis

GroupD03, ****33, N


This is a laboratory to simulate an ADC DAC set up with ramp and sine test. Using Ideal and Real test set up
This laboratory exposes the student to various tools which could be used for ADC and DAC data analysis

ADC DAC Schematic

The schematic shown is a 4 Bit ADC and DAC combined circuit.
A ramp and a Sine signal shall be inputed into the circuit and analysis done to investigate DNL, INL, FFT and Histogram Test
In the .save command, Vout was saved as the last value to ensure that a postprocess is possible on it, when its raw file is extracted.
A ramp voltage command "V1 In1 0 PULSE(0 1 0 655.36u 655.36u 0 1310.72u)" was generated and this was used for the ramp signal test
A sine signal command is also present "V2 in1 0 SINE(0.5 0.5 16784.66796875)", this was used for the sine test
During the ramp test, the sign signal is deactivated and during the sine test the ramp signal is deactivated

Ramp Test-Simulation,Raw Data Extraction and Integer Mapping

A ramp signal was inputed into the test circuit and the output signal was observed to be a series of 16 steps as seen in figure 1 below
The simulation generated a raw file;4Bit_ADC_DAC_pipe.raw
The generated raw file was fed into a data analysis program ("Read Raw File"-Check Reference for software link)
Data was extracted from raw file
Analysis was done over the total simulation time (655.36µs), with a time step value evenly distributed among the 16steps (i.e. 40.96µs)
Graph in figure 2, shows the resulting DAC curve. Each Code gets exactly one value.
Graph in fig 3 shows the the voltage levels mapped to integer numbers from 0 to 15

Figure 1

Figure 2 Figure 3

Ramp Test- DNL, INL Analysis

Using the data analysis software, the DAC DNL and INL analysis was done and the result is seen in Figure4
Extracted values were compared with Ideal values
No mismatch was observed
DNL and INL gives zero values throughout
No error in the DAC Curve
DAC Curve is ideal

Figure 4

Ramp Test- Histogram Test

The time step was changed from 40.96µs to 5.12µs so that we have several occurences per step
The raw file was reloaded and the DAC curve formed is shown in Figure 5
Since the time step was reduced, the number of sample occurences of each step became 8 instead of one as in the DNL-INL Test carried out above
Extracted Values were mapped to integer (0 to 15)
ADC Histogram test was done
The INL and DNL was observed to be zero, Figure 6

Figure 5

Figure 6

Sine Test

The Ramp input voltage was deactivated and the Sine input Voltage activated
Simulation was done and the output waveform is shown in Figure 7
Using the data analysis program, the raw file was extracted
Step size of 5.12µs was maintained and the resulting graph is shown in Figure 8
Extracted Values were mapped to integer (0 to 15)
ADC Histogram test was done and result shown in fFigure 9

Figure 7 Figure 8

Figure 9

Sine Test-FFT

Extracted Values were mapped to integer
Integer values were copied to the FFT data processing program interface (Check Reference for Link)
Values were pasted in the 'input' data box
'Read Positive Integer Data' tab was clicked
Number of points were ascertained to be 128 (total nuber of points with a step time of 5.12µs, in a simulation time of 655.36µs
'Generate Chat(Signal, FFT, INL,DNL)' tab was clicked
FFT data was displayed, as shown in figure 10
Histogram Test data for INL and DNL was also displayed as shown in Figure 11
Figure 10 Figure 11

Sine Test-SQNR, ENOB

Signal to Noise information was also computed and displayed by the program, Figure 12

Signal Magnitude was seen to be 11.87dB, while total Noise is -13.89dB

Using below equations;

Signal Magnitute - Total Noise = SQNR

SQNR = 6.02NdB + 1.76dB
where N= ENOB

The effective Number of Bits was calculated to be 4Bits as against 10Bits which was initially used for the FFT computation
Number of bits was adjusted to 4 and the 'Generate Chat(Signal, FFT, INL,DNL)' tab was clicked again
The Signal to noise data was unchanged.
The FFT and Signal scatter plot was unchanged
The Histogram test plot for INL and DNL was changed, as shown in Figure 13
Some errros were introduced as some points were above or below the zero point
Figure 13

Simulation R2R DAC-Sine Test

A R2R DAC Test setup was done as show in Figure 14
The Vout of our initial ideal DAC setup was deactivated and the Vout from the real R2R setup was activated
The Resistor values for R6 and R9 were adjusted so that an error is introduced to the setup
Simulation was done with Sine input signal
The FFT analysis program was used to investigate the FFT and Histogram test (DNL and INL)
The scatter plot of the outcome of the FFT analysis of the sine signal is shown in Figure 15
Signal to Noise data (Figure 16) shows that one bit was lost as a result of the error (ENOB=3)
Simulation was done with Ramp input signal
The data analysis program was used to investigate DNL and INL as seen in Figure 15

Figure 14

Figure 15

Figure 16

Simulation R2R DAC-Ramp Test

Simulation was then done on the R2R setup with a Ramp input signal
The data analysis program was used to investigate the Ramp signal
Time step was chosen as 40.96µs, so that each step has just one value
The extracted value was mapped to integer and the DAC INL,DNL Analysis tab was clicked to give the scatterplot for the DNL,INL data
Figure 17 potray's the results gotten
Figure 17

Challenges and Resolutions

[1]Initially, my Histogram INL-DNL scatter plot for my Sine test was incorrect, the final code was not at zero point. However, after Professor worked on the FFT data processing program, this was rectified.
[2]After the program was adjusted, I could not use firefox to do my FFT analysis; as the Number of bits showed 129 instead of 128 when I pasted the integer values. I had to use google chrome to do my FFT analysis.


[1]This laboratory has exposed me to some easy to use programs which could be used for DAC and ADC data analysis.
[2]It was observed that with an introduction of a R2R which has evenly distributed resistances, the response of my ADC was similar to that of an Ideal case.
[3]When an R2R structure was altered; by altering the resistance values, so they dont follow the regular pattern(which represents a real senerio), errors were introduced, which could be observed in the DNL-INL scatter plot.


[1] Making of a Webreport , Vollrath
[2] Read Raw File, Vollrath
[3]FFT Data Processing, Vollrath