Microelectronics

05 IC Manufacturing

Prof. Dr. Jörg Vollrath

04 Inverter

Video of lecture 05 19.04.2021

Länge: 40:00

0:0:50 From silicon to chip

0:1:37 Status Semiconductor Manufacturing

0:7:40 Wafers and Lots

0:11:57 Wafer Map 64 MBit DRAM

0:14:10 Perfect chips, DC good, functional, repairable

0:15:23 Chip Area, chips per wafer

0:21:10 Cost per chip, Yield, absolut, relative

0:24:40 Contact fails

0:26:40 Defect density on wafer

0:28:20 Defect density, chip size, yield, cost

0:34:55 A Memory Chip 1997

0:37:20 Cross Section of Microprocessor Chip

Video of lecture 05 21.04.2021

Länge: 40:00

0:0:0 Delay Times

0:2:55 Preferences SPICE parasitics

0:5:55 RC Delay

0:7:30 Video process

0:12:33 Wafer carcass

0:16:0 Test cost and duration

0:19:30 450mm wafers not yet

0:21:0 Pattern transfer with photo mask

0:23:19 CMP, cleaning, thermal anneal

0:25:14 CMOS Manufacturing process animation

0:26:40 Alignment marks

0:28:40 n-well

0:29:40 Polysilicon

0:31:40 Metal

Overview

Review:

MOSFET switch
Propagation delay
Inverter
Pass gate and transfer gate

Today:

From silicon to a chip
Wafer, lot, yield, defect density
Process steps: (deposition), photo mask, etch/implant, mask removal, (deposition), planarization (cmp)
Challenges in manufacturing: Volumne and number of process steps, defects, process variations
Unit transistor: FinFET

Reading:

Status semiconductor manufacturing 2017

Design und Elektronik 3/2017 Semiconductor Manufacturing:

Leading players: Intel, Samsung, TSMC

Topic	28 nm	14 nm
Design cost	30 Mio. $	80 Mio. $
Metal layers	11
Wafer cost	3500.-$	4800.-$ per wafer
Duration	2.5 months, 68 days for 52 photo masks 1 week package and test	66 photo masks, 3 months

Book about microprocessor design: The Pentium Chronicles

Challenges of Semiconductor Manufacturing

High number of processign steps:
66 Masks, each mask needs 5..15 steps
High number of wafers per month:
High number of chips per wafer: 1000..10 000
Manufacturing takes 2..3 month
Manufacturing planning

Fastest flow with high throughput

Manufacturing control

Data collection
Traceability: Wafer id, chip id
Process control, process capability

Fully automated manufacturing
Big Data

Wafers and lots

Silicon wafer
300mm diameter
Rectangular chips
Defects
25 Wafers are one lot
Processed wafer cost ~ 1000..2000 $
Mask set: 10k..1M $
For a given defect density an optimum chip size can be calculated

1 Lot: 25 Wafers

Wafer are specified by diameter. A 200mm wafer has a radius of 100mm.
300mm, 8" ≈ 200mm, 6", 4", 3".

https://en.wikipedia.org/wiki/Wafer_(electronics)

Wafer map 64 MBit memory chip (1997)

Number of Chips per Wafer:
38*20 – 2 *(1+1+2+4+5+7+10+16)
- 2 *(1+2+3+5+7+9+13) = 760 – 172 = 588

Die Area Estimation 200mm wafer diameter:
π * r *r /(number of chips)

31416 mm² / 588 = 53.4 mm²

Technology 0.24 μm
8F² Cell, 64 MBit
Array Size :
64 MBit * 8 * 0.24 * 0.24E-6 mm² = 30.1 mm²

Cell Efficiency :
Memory cell area / Die size =
30.1/53.4 = 56.4 %

Year: 1996

Yields:

Absolute yield:
$ Y = \frac{N_{Good}}{N_{Total}} $

Perfect yield: White chips
$ Y_{perfect} = \frac{7}{576} = 1.18 \% $

Example: Defect density and chip size

4 black defects, 4 blue defects, 8 pink defects
Size A, 4 A, 16 A

Example: Defect density and chip size

300mm wafer

Chip area	Defects, Good chips, Yield, cost per good chip			Chips per wafer, minimum cost per chip
Chip area	4	8	16	Chips per wafer, minimum cost per chip
A = 68 mm²	454, 99%, $2	450, 98%, $2	442, 96%, $2	458, $2
4 A = 274 mm²	98, 96%, $10	94, 92%, $11	87, 88%, $12	102, $10
16 A = 1097 mm²	20, 84%, $50	16, 66%, $62	9, 33%, $111	24, $40

With larger area the cost per chip increases non linear.
Larger chip area leads to wafer area loss at the edge.

Chip size of 100 mm² is optimum.

A memory chip 1997

Cross-section of microprocessor chip

Courtesy of International Business Machines Corporation. Unauthorized use not permitted.

Cross-section of 64-bit high-performance microprocessor chip

Date added: 05 Dec 2005

Cross-section of 64-bit high-performance microprocessor chip built in IBM's 90 nm Server-Class CMOS technology with Cu/low-k wiring.
Above the transistors, the wiring levels include one W local interconnect, five "1x-scaled" Cu levels in full SiCOH low-k dielectric, three "2x-scaled" Cu/SiCOH levels, two "6x-scaled" Cu levels in FTEOS/SiO2 dielectric, and finally, one Al(Cu) terminal pad and wiring level.
The minimum M1 Cu line widths and spaces are 0.12 um.

Process steps

Pattern transfer with photo mask

The wafer is coated with photo resist. The pattern of a mask is transfered via light into the photo resist. The illuminated photo resist changes properties and is selectively removed.
Photolithography

Deposition

Oxide, nitride or metal can be deposited uniformly onto the wafer.

Etch

There is chemical or plasma etch possible to remove material selectively.

Implant

Dopant ions (phosphor, boron) are electrically accelerated and shot into the wafer.
After annealing at high temperature the dopants are activated.

Process steps continued

CMP chemical mechanical polishing

"Chemical mechanical polishing/planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces." Wikipedia

Chemical cleaning

Between manufacturing steps cleaning procedures are applied to increase yield.

Thermal anneal

High temperature steps are necessary to activate dopants.

All steps are monitored to be able to trace a bad product to the root cause.

Video Intel: From Sand to chip
Presentation
Video Infineon: Chip Manufacturing - How are Microchips made? Start 6:45-11:30

CMOS Manufacturing process

Top view:

Cross section:

Learning outcome

There will be always defects and faults
Test, diagnostics and traceability are very important
High volume manufacturing is a challenge
PCB design can learn from microelectronics

2019 03 01 05 IC Manufacturing Microelectronics Prof. Dr. Joerg Vollrath

Microelectronics

05 IC Manufacturing

Prof. Dr. Jörg Vollrath

Video of lecture 05 19.04.2021

Video of lecture 05 21.04.2021

Overview

Status semiconductor manufacturing 2017

Challenges of Semiconductor Manufacturing

Wafers and lots

Wafer map 64 MBit memory chip (1997)

Yields:

Example: Defect density and chip size

Example: Defect density and chip size

A memory chip 1997

Cross-section of microprocessor chip

Process steps

Pattern transfer with photo mask

Deposition

Etch

Implant

Process steps continued

CMP chemical mechanical polishing

Chemical cleaning

Thermal anneal

CMOS Manufacturing process

Learning outcome

Next: