Microelectronics06 Design RulesProf. Dr. Jörg Vollrath05 Manufacturing Process |
Länge: 01:02:59 |
0:1:23 Chip cross section REM picture 0:4:18 Bad oxide thickness, bad contact 0:6:54 Top view defects 0:10:24 Cross section doping REM 0:11:12 Reverse Engineering and competitor analysis 0:14:38 NAND Chip analysis, technology, size, capacity 0:18:23 Matching schematic versus layout 0:21:10 Layout LTSPICE AD, AS, PD, PS added capacitance 0:22:18 Schematic LTSPICE bare transistor model 0:23:42 MOSIS Design rules 0:28:43 Electric Preferences Technology Design Rules 0:32:48 From circuit to chip 0:36:1 Inverter mask set with alignment marks 0:39:48 Inverter Alignment 0:40:35 Pattern transfer, small feature size, shape, neighborhood 0:45:22 REM picture with rounded features of material 0:47:18 Dummy shapes 0:48:28 Overetch 0:49:28 Underexposure 0:51:34 Manual design rule check example 0:59:28 Extracting the schematic from layout 1:2:38 Logic function truth table extraction 1:5:18 LTSPICE simulation of truth table 1:8:38 LTSPICE PULSE statement 1:11:38 Learning Outcome |
Symbols: Transistor, gnd, Vdd Properties: Names, width, length |
Layers, different color: Connection: metal (blue), polysilicon (orange,pink), contact (black) Transistor: crossing polysilicon and n- or p-diffusion (green) |
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In2 | In1 | Out |
0 | 0 | 1 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |