# Microelectronics

06 Design rules

## Video of lecture 07 12.05.2021

 Video is not visible, most likely your browser does not support HTML5 video Länge: 1:11:13 0:0:0 Overview Parasitics and design style 0:1:20 Devices outline 0:3:20 Resistance 0:5:50 Temperature and resistance of doped silicon 0:8:50 Sheet resistance 0:13:50 Layout of resistors 0:16:50 Contact resistance 0:18:30 Maximum current density 0:22:52 Supply voltage routing 0:26:53 Capacitances 0:31:30 Example poly silicide resistor capacitance 0:33:56 Example resistance and capacitance 0:38:25 Square counting C 0:43:29 Resistance 0:49:36 Half a square 0:40:52 Cross section

## Video of Silicon compiler 10.05.2021

 Video is not visible, most likely your browser does not support HTML5 video Länge: 1:28:22 0:0:0 0 0:0:44 Schematic 0:2:46 Silicon compiler 0:4:10 Delete some VHDL 0:5:23 Run Tools Silicon compiler 0:7:36 Error: Select M1 in another layout
Curve fitting for MOSFET
Measuring MOSFET parameters

# Overview

Review:

• Alignment
• Design rules
• Stick diagram

Today:

• Resistance R
• Capacitance C
• RCX tool
• Electromigration
• AOI and TG design style

# Devices Outline

 Resistor Capacitance p-n junction: Diode MOS Transistor
MOSFETs are the building blocks of circuits.
There are also resistors and capacitances, which can be realized with transistors.
Sometimes circuit peformance is limited by parasitics.
The layout above shows an input with along polysilicon line leading to an inverter.
There will be extra propagation delay because of the R and C of the polysilicon.
For real simulations of circuits parasitic R and C are extracted from layout and used.
An equivalent schematic with R and C and some parasitics diodes are shown below.
This lecture deals with resistors and capacitances in semiconductor technology.

# Resistance

 $R = \frac{\rho}{t} \frac{L}{W} = R_{square} \frac{L}{W}$ R: resistance ρ : resistivity t: thickness L: length W: width Rsquare: sheet resistance $\rho = f(\mu_n, \mu_p, n(N_A), p(N_D), T)$ μn, μp: mobility of electrons and holes ND, NA: doping concentration T: temperature non linear relationship

# Resistance of doped silicon

## Doping dependence

Thickness 180µm, Sheet Resistance calculator, PV Lighthouse
 Doping concentration 1e+15 3e+15 1e+16 3e+16 1e+17 3e+17 1e+18 3e+18 1e+19 3e+19 1e+20 n-sheet resistance 360000 102000 30500 11200 4210 1940 920 485 233 109 42.6 p-sheet resistance 1.069e+06 299000 86500 30100 10300 4280 1820 888 398 178 66.4

# Sheet resistance values

 Layer Sheet resistance(Ω/square) TCR1 (ppm/C) VCR1 (ppm/V) Mismatch % dR/R n-well 500±10 2400±50 8000±200 <0.1 n+-poly 200±1 20±10 700±50 <0.5 p+-poly 400±5 160±10 600±50 <0.2 n+ 100±2 1500±10 2500±50 <0.4 p+ 125±3 1400±20 80±80 <0.6

Reference: CMOS, Circuit Design, Layout and simulation, Baker, Chap. 4, p.88

# Layout of resistors

 Avoiding long lines Serpentine Avoid corners with extra contacts Count number of squares along resistor and multiply with sheet resistance: 27 squares N-poly silicide: 5Ω/square R = 27 * 5 Ω = 135 Ω

# Contact Resistance

 10Ω/contact Unit contacts More contacts are better Parallel connection $R_{total} = \frac{R}{n}$

# Maximum current density and electromigration

 Metal: Electromigration 1..2mA/µm Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size in electronics such as integrated (ICs) decreases, the practical significance of this effect increases.

# Supply voltage routing

 0.1 Ω/square AreaChip = 100 mm2 Line length up to 10 mm. 200 nm width of line. 50 000 squares R = 5 kΩ Current: 40 µA; Voltage drop: Vdrop = I * R = 0.2 V VDD = 1 V Vinverter = 1 V - 2 * 0.2 V = 0.6 V Vthn = 0.3 V; Vthp = -0.3 V;

# Capacitances

 Layer Plate Capacitance aF/µm2 Fringe Capacitance aF/µm N-well to substrate 100±20 300±60 Poly to substrate 58±5 88±4 Metal1 to poly 39±4 88±4 Metal1 to substrate 23±2 79±4 Metal2 to poly 18±2 87±4 Metal2 to metal1 39±4 88±4

Reference: CMOS, Circuit Design, Layout and simulation, Baker, Chap. 4, p.61
• Area capacitance: plate capacitance
$C = \epsilon_0 \cdot \epsilon_{SiO2} \frac{A}{d}$
ε dielectric constant
A: plate area
d: distance between electrodes, thickness of isolator
• Fringe capacitance

# Example poly silicide resistor

 Avoiding long lines Serpentine Avoid corners instead use extra contacts Count number of squares along resistor and multiply with sheet resistance: 27 squares N-poly silicide: 5Ω/□ R = 27*5 5Ω = 135 5Ω Capacitance to ground: Area and fringe C = F * F * 27 * Cpl + F * 56 * Cfr Distributed R C Circuit

# Example Inverter

 Peak current Parasitic R,C Max number of inverters on the power supply? Max current: 6.8 µA, 33 µA Polysilicon: Squares: (17 + 6*30 + 17 + 3) □ R = 217 □ R□ = 217 * 6.2 Ω = 1344 Ω C = 217 * CArea + 434 * Cfringe C = 217 * 0.15 * 0.15 µm2 * 0.15 fF/µm2 + 434*0.15 µm *0.06 fF/µm = 0.73 fF + 3.9 fF

## Design Tool RCX

• Resistor and capacitance extraction from layout
• Electric: Preferences, Tools, Technology, SPICE
• More realistic delays
• More realistic power distribution
• More simulation time

# Example

 A top view of a metal line in a 50nm process running from A to B is shown crossing a polysilicon line, which runs from left to right. The metal sheet resistance is Rsquare=0.6Ω/square. The lines are isolated with 80nm oxide. (ε0= 88 fF/cm, εSiO2 = 4) 1. Calculate the capacitance between the metal line (blue) and the polysilicon line (yellow).(2 points) 2. Calculate the resistance from A to B? (2 points) 3. Calculate the voltage drop on the line if a current of 30µA is flowing. (2 points) 4. Draw a cross section from points C to D (4 points)

# MOSFET used for other purposes

 Capacitance Resistance Diode Lateral bipolar transistor

# NFET Transistor roll-off

MOSFET threshold voltage is changing with device length for small feature size.

The graph is generated simulating 50nm NFETs with a transistor model from Baker.
Threshold voltage is depending a lot on transistor length. A dramatic decrease of threshold voltage below 50nm can be seen. A plateau of threshold voltage is around 65 nm length. Threshold voltage can be engineered with doping profile. Therefore it is assumed the transistor models are from a 65 nm process.
For measurement transistors with different length are designed.
A fixed current scaled by the W/L ratio is used for each transistor and measured gate source voltage is the threshold voltage. Ouput of LTSPICE simulation:
ISX = -1
L [nm]	I [uA]
40	-0.75 M11	V(z):	0.0205882	 voltage
50	-0.6  M1 	V(a):	0.298814	 voltage
55	-0.54 M9	V(y):	0.341268	 voltage
60	-0.5  M2	V(b):	0.360567	 voltage
70	-0.42 M12	V(x):	0.369853	 voltage
80	-0.37 M3	V(c):	0.364348	 voltage
100	-0.3  M4	V(d):	0.343594	 voltage
120	-0.25 M5	V(e):	0.323484	 voltage
150	-0.2  M6	V(f):	0.300119	 voltage
200	-0.15 M7	V(g):	0.275101	 voltage
240	-0.12 M8	V(h):	0.262334	 voltage
300	-0.1  M10	V(j):	0.234942	 voltage


# MOSFET and FINFET

## FINFET

Feature size sub 25 nm
Fixed transistor width
Channel surrounded by gate

# Nanosheet Transistor (2021)

## Nanosheet

NFET and PFET on top of each other

## FINFET

Fixed transistor width
Channel surrounded by gate
Feature size < 5nm
Name: gate-all-around, multibridge channel, nanobeam, nanosheet

The Nanosheet Transistor Is the Next (and Maybe Last) Step in Moore’s Law?

# Stick diagram 3-input NAND

 Use lines to draw a circuit Blue metal Green SD area Red: Gate Black cross for contacts Start with VDD in metal at top and gnd at bottom Add transistors

# AOI design style

## NAND

$Y = \overline{ X1 \cdot X2 \cdot X3}$

## NOR

$Y = \overline{ X1 + X2 + X3}$
PFETs connected to VDD are at the top and NFET connected to GND at the bottom.
A NAND has PFETs on the top in parallel and NFETS at the bottom in series.
A NOR has PFETs on the top in series and NFETS at the bottom in parallel.
This can be used for arbitrary functions.
There can be additional inverters added to the inputs or outputs to realize a logic function.

# AOI design style example

 $Y = \overline{ (a + b) \cdot c}$

# Truth table and Sum of Products (SoP)

Truth table:
 Inputs Outputs AND Operations S0 S1 Y Y1 Y2 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 1 1 0 0 0
Any truth table can be composed as sum of products.
$Y = Y1 or Y2 = (/S0 and S1) or (S0 and /S1)$ $Y = (/S0 \cdot S1) + (S0 \cdot /S1)$
The and and or operation can be replaced with NAND operations.
$Y = \overline{ \overline{( /S0 \cdot S1 )} \cdot \overline{( S0 \cdot /S1 )}}$

# Multiplexer and Demultiplexer

A multiplexer transfers one of n lines to the output.
A demultiplexer transfers one input signul to one of n output lines.
Multiplexer and Demultiplexer can be realized using switches (TG).
Switches limit the drive strength of the output.
A multiplexer can be also realized with standard logic.
A demultiplexer should have a tristate output.

One line of X0, X1, X2, X3 is connected to Y. S0 and S1 are the select lines.
MUX
 S0 S1 Y 0 0 X0 0 1 X1 1 0 X2 1 1 X3
DEMUX
 S0 S1 X0 X1 X2 X3 0 0 Y Hi-Z Hi-Z Hi-Z 0 1 Hi-Z Y Hi-Z Hi-Z 1 0 Hi-Z Hi-Z Y Hi-Z 1 1 Hi-Z Hi-Z Hi-Z Y

# Implementation of bigger truth tables

Provide all 16 possible 2 input functions.
Use a multiplexer for additional inputs.
Example: LUT4_37E5
 X1 X0 LUT20 LUT21 LUT22 LUT23 LUT24 LUT25 LUT26 LUT27 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0
 X1 X0 LUT28 LUT29 LUT2A LUT2B LUT2C LUT2D LUT2E LUT2F 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

The picture shows implementation of a 4 input truth table.
Inputs are I0,I1,I2,I3.
 Nr I3 I2 I1 I0 Y Hex 0 0 0 0 0 1 5 1 0 0 0 1 0 2 0 0 1 0 1 3 0 0 1 1 0 4 0 1 0 0 0 E 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 7 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 0 12 1 1 0 0 1 3 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 1 0
This is implemented in sclib.jelib

# Tri-state Driver

Multiple drivers can be connected to a bus to save wiring and space.
Then a tri-state driver is needed.
Here 2 implementations are shown.
A transfer gate after the driver has a lower output resistance.

 EN Y 0 Hi-Z 1 A
 EN A Y 0 0 Hi-Z 0 1 Hi-Z 1 0 0 1 1 1

# Summary

• Draw a NAND and NOR truth table, schematic and layout.
• Construct the boolean function from the truth table
• What is the AOI style?
• What does AOI stand for?
• Draw the AOI schematic and layout of a given boolean function.
• Calculate the delay of a given AOI style circuit.
• Why do you need other design styles?
• Do you know any other design styles?

Next: 08 System design and VHDL