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Länge: 0:55:04

0:0:0 Timing Closure and Delay

0:2:30 tDelay

0:7:30 Power consumption

0:13:30 Delay in and out

0:16:0 Delay equation with load L

0:17:43 Explanation of schematic

0:19:20 Delay equation with load L and driver W

0:21:20 Plotted graph discussion

0:26:37 Delay with second inverter, 2 stages

0:28:10 Explanation of delay

0:29:16 tDelay with 2 stages

0:32:22 Final equation

0:34:43 Graph discussion

0:39:25 Unit transistor scaling with number of inputs

0:41:53 Question

0:44:57 Equation start

0:47:23 Graph discussion

0:49:59 Simplistic model no output capacitance

0:53:5 Calculation of delay in JavaScript

Overview

Review:

Unit transistors, cell layout

System synthesis

VHDL entity and architecture

Today:

VHDL, VHDL books

ASIC, FPGA, microprocessor

Delay and Timing Closure: Inverter sizing, pipeline

Systems

FPGA

Field programmable gate array (FPGA)

Programmable

Switch matrix

Logic

Registers

Blocks: Multiplier, adder, RAM

Microprocessor

Design entry

VHDL, Verilog

Schematic

State diagram

Matlab, Labview

Switch matrix, logic and registers, programmable

Xilinx FPGA configurable lookup table

Logic, register (folder: netgen/synthesis

curr_zero_not000125 : LUT4
generic map(
INIT => X"135F"
)
port map (
I0 => curr_ir(3),
I1 => curr_ir(2),
I2 => curr_acc(3),
I3 => curr_acc(2),
O => curr_zero_not000125_120
);
Logic:
AND INIT => X“8000“
OR INIT => X“FFFE“
RAM: I0..I3: address

Books: FPGA Programming and VHDL

Rapid Prototyping of Digital Systems:

Quartus® II Edition
Hamblen
71.- Euro

FPGA Prototyping by VHDL Examples:

Xilinx Spartan-3 Version
Chu
68.99.-Euro

No cost VHDL compiler and simulator:
FPGA vendors: Intel(Altera), Xilinx
Xilinx WebPack free to download

Microelectronics Design Optimization

Technology:

FPGA, Gate Array, Standard cells, Full custom

Design

SystemC, VHDL/Verilog (RTL), Schematic

Block technology:

CPU, State machine

Synchronous logic, asynchronous logic

Memory: SRAM, RAM, NAND Flash

CMOS logic style

AOI, dynamic, transfer gate (TG), dynamic CMOS, domino

Layout style

Regular, full custom, transistor sizing

Goal: Time to market, timing and propagation delay, power, area

Gate Array, Semi-Custom, and Full-Custom ICs

Gate Array (biggest): Everything is prefabricated except metal connection
Standard cells: Logic cells are placed and routed
Full custom (smallest): Each gate is individually drawn and routed.

Area ratio: 3:2:1

Timing Closure and Propagation Delay

Measuring propagation delay requires a real driver to measure the influence of input capacitance
and a real capacitance load to be charged. In the center is the DUT (device under test).

Propagation Delay:
\( t_{delay} = 0.7 R C_{tot} \)
R: on resistance of PFET/NFET R_{on};
C: load capacitance

Changing W_{p}/W_{n}
Input capacitance changes,
R_{on} changes
Smaller R_{on} and bigger input capacitance
How to optimize timing performance?

Timing closure
No premature optimization!
Start with minimum size, identify timing limit and then optimize.

Propagation Delay

Propagation Delay

Source inverter, DUT and load inverter minimum size: R, C

t_{delay} = t_{delayin} + t_{delayout}
= 0.7 R C_{DUTin} + 0.7 R_{DUTon} C

No change in speed, higher power consumption, more area

Topology and Propagation Delay

Inverter chain

Load: Driving a line or multiple logic gates

Transistors in series or parallel

Propagation Delay and Load

Load (L): Driving a line or multiple logic gates
t_{delay} = t_{delayin} + t_{delayout}
= 0.7 R · (W · C) + 0.7 (R/W) (L · C)
t_{delay} = t_{delay0} ( W + L/W)

Delay with large loads can be reduced with width W.
Using unit transistors W should be an integer number.

t_{delay}(L=1) = t_{delay} ( W + 1/W)
t_{delay}(L=5) = t_{delay} ( W + 5/W)
t_{delay}(L=10) = t_{delay} ( W + 10/W)

Power

P_{AVG}= V_{DD} · I_{AVG}
Current is needed to charge and discharge capacitances.
\( C = \frac{Q}{V} = \frac{I \cdot t}{V} \)
\( I = \frac{C \cdot V}{t} = C \cdot V_{DD} \cdot f_{CLK} \)
P_{AVG}= V_{DD}^{2} · C · f_{CLK}

This is the active power consumption.
There are also cross currents from VDD to gnd during switching and transistor leakage currents.

Propagation Delay and Load

Load: Driving a line or multiple logic gates with 2 stages
t_{delay} = t_{delayin} + t_{mid} + t_{delayout}
= 0.7 R W C_{DUTin}
+ 0.7 R_{DUTon}/W W * W C
+ 0.7 R_{DUTon}/W/W L C
= t_{delay} ( W + W + L/W/W)

L: Load, W: Width
For higher loads use more than one stage.

Propagation Delay and Logic function

N transistors in series in logic block
t_{delay} = t_{delayin} + t_{delayout}
= 0.7 R W C_{DUTin}
+ 0.7 N R_{DUTon} / W * C * L
= t_{delay} ( W + N / W * L)

Change only width W of series transistors
t_{delay1} = t_{delayin} + t_{delayout}
= 0.7 R (0.5 + 0.5 W ) C_{DUTin}
+ 0.7 N R_{DUTon}/ W C * L
= t_{delay} ( 0.5 + 0.5 * W + N / W *L )

Propagation Delay and Pipelines

What is the maximum clock frequency?
t_{pd} = 5 ns, t_{setup} = 1 ns