Overview

• Unit transistors, cell layout
• System synthesis
• VHDL entity and architecture

• VHDL, VHDL books
• ASIC, FPGA, microprocessor
• Delay and Timing Closure: Inverter sizing, pipeline

Systems

FPGA Field programmable gate array (FPGA) Programmable Switch matrix Logic Registers Blocks: Multiplier, adder, RAM Microprocessor Design entry VHDL, Verilog Schematic State diagram Matlab, Labview

Switch matrix, logic and registers, programmable

Xilinx FPGA configurable lookup table

Logic, register (folder: netgen/synthesis

curr_zero_not000125 : LUT4 generic map( INIT => X"135F" ) port map ( I0 => curr_ir(3), I1 => curr_ir(2), I2 => curr_acc(3), I3 => curr_acc(2), O => curr_zero_not000125_120 ); Logic: AND INIT => X“8000“ OR INIT => X“FFFE“ RAM: I0..I3: address

Books: FPGA Programming and VHDL

Rapid Prototyping of Digital Systems: Quartus® II Edition Hamblen 71.- Euro FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version Chu 68.99.-Euro

Microelectronics Design Optimization

• Technology:
• FPGA, Gate Array, Standard cells, Full custom
• Design
• SystemC, VHDL/Verilog (RTL), Schematic
• Block technology:
• CPU, State machine
• Synchronous logic, asynchronous logic
• Memory: SRAM, RAM, NAND Flash
• CMOS logic style
• AOI, dynamic, transfer gate (TG), dynamic CMOS, domino
• Layout style
• Regular, full custom, transistor sizing
  

• Goal: Time to market, timing and propagation delay, power, area

Gate Array, Semi-Custom, and Full-Custom ICs

Gate Array (biggest): Everything is prefabricated except metal connection Standard cells: Logic cells are placed and routed Full custom (smallest): Each gate is individually drawn and routed. Area ratio: 3:2:1

Timing Closure and Propagation Delay

Measuring propagation delay requires a real driver to measure the influence of input capacitance and a real capacitance load to be charged. In the center is the DUT (device under test).

• Propagation Delay:    \( t_{delay} = 0.7 R C_{tot} \)
  R: on resistance of PFET/NFET R_on;    C: load capacitance
• Changing W_p/W_n
  Input capacitance changes, R_on changes
  Smaller R_on and bigger input capacitance
  How to optimize timing performance?
  

Timing closure
No premature optimization!
Start with minimum size, identify timing limit and then optimize.

Propagation Delay

• Propagation Delay
• Source inverter, DUT and load inverter minimum size: R, C
• t_delay = t_delayin + t_delayout = 0.7 R C_DUTin + 0.7 R_DUTon C
• R: on resistance of PFET/NFET
• C: load capacitance
• Changing all Wp/Wn
• Increasing width: R_new= R/2, C_new= 2 C
• t_delay = t_delayin + t_delayout = 0.7 R/2 2 C_DUTin + 0.7 R_DUTon/2 2 C
• No change in speed, higher power consumption, more area

Topology and Propagation Delay

Inverter chain
Load: Driving a line or multiple logic gates
Transistors in series or parallel

Propagation Delay and Load

Load (L): Driving a line or multiple logic gates
t_delay = t_delayin + t_delayout = 0.7 R · (W · C) + 0.7 (R/W) (L · C)
t_delay = 0.7 R · C ( W + L/W) = t_delay0 ( W + L/W)

Delay with large loads can be reduced with width W.
Using unit transistors W should be an integer number.

t_delay(L=1) = t_delay ( W + 1/W)
t_delay(L=5) = t_delay ( W + 5/W)
t_delay(L=10) = t_delay ( W + 10/W)

Power

P_AVG= V_DD · I_AVG
Current is needed to charge and discharge capacitances.
\( C = \frac{Q}{V} = \frac{I \cdot t}{V} \)
\( I = \frac{C \cdot V}{t} = C \cdot V_{DD} \cdot f_{CLK} \)
P_AVG= V_DD² · C · f_CLK

This is the active power consumption.
There are also cross currents from VDD to gnd during switching and transistor leakage currents.

Changing W to larger values increases power consumption.

Propagation Delay and Load

Load: Driving a line or multiple logic gates with 2 stages
t_delay = t_delayin + t_mid + t_delayout = 0.7 R W C_DUTin + 0.7 R_DUTon/W W * W C + 0.7 R_DUTon/W/W L C = t_delay ( W + W + L/W/W)

L: Load, W: Width
For higher loads use more than one stage.

Propagation Delay and Logic function

N inputs: N transistors in series in logic block
t_delay = t_delayin + t_delayout = 0.7 R W C_DUTin + 0.7 N R_DUTon / W * C * L = t_delay ( W + N / W * L)

Change only width W of series transistors
t_delay1 = t_delayin + t_delayout = 0.7 R (0.5 + 0.5 W ) C_DUTin + 0.7 N R_DUTon/ W C * L = t_delay ( 0.5 + 0.5 * W + N / W *L )

Propagation Delay and Pipelines

What is the maximum clock frequency?
t_pd = 5 ns, t_setup = 1 ns

Longest path: t_cycle > 5*t_pd+t_setup = 26 ns; f = 38MHz

Longest path: t_cycle > 3 * tpd _{+ tsetup = 16 ns; f = 62.5MHz}

Retiming of synchronous logic

FPGA Timing

• Provide VHDL code to realize pipeline
  Registers only
• Retiming done by compiler
• Input CLK should use internal PLL to avoid setup and hold issues

Summary

• Design strategy
• FPGA, gate array, full custom design

• High level language (SystemC, VHDL) and synthesis of layout

• Timing closure
• Transistor resizing
• Additional drivers
• Logic transistor resizing
• Pipeline