Hochschule Kempten      
Fakultät Elektrotechnik      
Microelectronics       Fachgebiet Elektronik, Prof. Vollrath      


08 System, Synthesis, VHDL

Prof. Dr. Jörg Vollrath

07 CMOS Logic

Video of lecture 09 (12.05.2021)

Länge: 1:30:00
0:0:0 Review

0:1:15 MOSFETs for other purposes

0:5:3 Function to layout

0:6:56 AOI style

0:12:45 Output capacitance and layout

0:16:56 Delay

0:20:16 Truth table

0:24:24 AOI design style

0:25:56 Sum of products (SOP)

0:30:17 Multiplexer, Demultiplexer and logic

0:39:16 Bigger truth table implementation

0:46:56 Tri-state driver

0:48:6 Chip layout

0:55:46 Design entry

1:0:49 Silicon compiler example

1:3:6 Tool chain

1:4:41 Silicon Compiler explore design space

1:6:31 Configurong silicon compiler

1:9:36 VHDL entity and ports

1:11:44 architecture, component, structural

1:15:4 Hierarchy and connection

1:18:37 Behavioral and structural VHDL

1:19:50 Wiring layers and area

1:22:40 VHDL overview

Video of Multiplier (17.05.2021)

Länge: 1:30:00
0:0:0 Multiplier

0:2:14 Example 2 2 bit numbers

0:6:10 Design options

0:11:59 Inputs and outputs, equations

0:16:9 Add2 operation LUT26, LUT28

0:18:59 LUT26 naming convention

0:22:59 Start library multiplier

0:23:46 Schematic

0:30:39 Make icon

0:32:14 Hooking up the subcircuits

0:36:44 Simulation

0:39:39 SPICE text

0:41:1 Pulse statements

0:42:14 Simulate SPICE

1:18:4 Setting up waveform display

0:44:12 Check output

0:46:34 Generate reference output

0:48:14 Tool silicon compiler

0:50:34 Change text size

0:51:44 LTSPICE layout simulation

Overview 2021


Next week laboratory:
From VHDL to layout

Integrated circuit design methods

Many tools and libraries are working together.
Data exchange is done through files.

Basic libraries

A library for a MIPS processor: muddlib07.jelib
Using "Silicon Compiler" with VHDL: sclib.jelib

Standard cell: NAND layout

Cell Discussion:
Width determined by number of input and outputs
Same height, names, vertical horizontal lines, exports, hierarchy

Layout 1-Bit Adder

library: muddlib_07
cell: fulladder
pins: a, b, cin, sum, cout

Very nice regular
Not area optimized
Standard cell
  • M2 used
    Vertical pink
  • Polysilicon
    Evenly spaced
  • M1

This is an example from a MIPS microprocessor.

Multiple cells: 4 Bit Adder Floorplan

Use grid for wiring

  • Metal 1:
  • Metal 2:
  • Cell input and output
    Different x and y coordinates
    Since Carry is propagated Cin and Cout have the same x coordinates

Manual planning, place and route for data path

Control circuits are at the top.
For each bit a row (bitslice) is taken with functionality of register, mux, alu.

Chip layout

Area is square to maximize area for a given number of pins at the edge.

Design Entry

  • Schematic

  • Layout

  • Graphical State machine

  • VHDL

  • SystemC

  • C/C++

Schematic and VHDL


The wiring of logic cells is done by routing M2 wires vertically below the cells and connecting these wires with horizontally running M1 wires.

Wiring Layers and Area

On the left is a automatically placed and routed layout.
Light blue metal1 M1 lines are used vertically, M2 lines are used horizontally.
Between strips/columns of logic cells the M1, M2 routing is placed.
More area is used for wiring than for active devices.
Having more metal layers for routing allows putting wiring on top of logic cells.
This is shown on the cross section on the left side, where 2 M1 lines are placed as M3 lines on top an the width of the layout is reduced.
The layout was generated with mod_m_counter layout.

Silicon Compiler Start

  • Select a schematic
  • Tools->Silicon Compiler -> Convert current cell to layout
  • Sclib is opened
    • Vhdl, net view are created
    • Error message
    • Modify vhdl view
      • Delete entities of subcircuits
      • Copy these subcircuit groups including layout to sclib
      • Delete ground, power component in vhdl or create it and modify signal list.

Silicon Compiler Continued

  • Error message:
    • SC Maker cannot find Horizontal Arc Metal-1 in technology artwork
    • Select a metal arc in a layout
    • Select vhdl do Silicon Compiler
  • Error: Exception
    Change number of rows and try again
  • Preferences -> Tools -> Silicon Compiler
    • Number of rows
    • Routing min active distance -9
    • Horizontal spacing

Silicon Compiler Finish

  • Preferences -> Tools -> Silicon Compiler
    • Number of rows
    • Routing min active distance -9
    • Horizontal spacing
  • A new silicon compiler run will create another layout
    • Nothing will be lost

VHDL overview

You do not need to know all details of VHDL!

Copy, paste, modify

VHDL Definition (Wikipedia)

VHDL Block (Entity) and Logic (Architecture)

  • Adder
  • Entity
    • Port
    • In, out
  • Architecture
    • Signal
    • Connection: <=
    • Operation; +
SUM = A + B    
entity Sum is
   port ( A : in STD_LOGIC_VECTOR (3 downto 0);
          B : in STD_LOGIC_VECTOR (3 downto 0);
          S : out STD_LOGIC_VECTOR (3 downto 0);
          C : out STD_LOGIC
end Sum;

architecture Behavioral of Sum is
signal o: STD_LOGIC; 
 S <= A + B;
end Behavioral;

Ports, Busses and Signals


  • Buses are used to save lines.
  • Time muxed signals are transmitted.
  • The driver is enabled via EN signal and has otherwise the state ‘Z‘.

signal IN_1,OUT_1,IN_2, OUT_2, MY_BUS: std_logic_vector(3 downto 0);
Signal EN_1;EN_2:std_logic;
IN_1 <= MY_BUS; IN_2 <= MY_BUS;
MY_BUS <= OUT_1 when EN_1= ‘1‘ else (others=>‘Z‘);
MY_BUS <= OUT_2 when EN_2= ‘1‘ else (others=>‘Z‘);
end Test;

Hierarchy and Connection

  • Use components
    • State the port definition
  • Declare signals
  • Use Components
    • by naming instance
      PFA0: PFA
    • By connecting input and outputs
      Port map ( name of original port => local signal name
architecture Behavioral of Sum is
 component PFA
      port( A: in STD_LOGIC;
            S: out STD_LOGIC);
  end component PFA;
signal o: STD_LOGIC; 
   port map (A=>A0, S=>o);
 S0 <= o;
end Behavioral;

State machine, process, incomplete if


  • Variable
  • Case statement
  • Truth table

  • Synchronous design
    Rising edge
  • Register
    Incomplete if statement
process (a_in, b_in) 
 variable state: STD_LOGIC_VECTOR(1 downto  0) 
 state := a_in & b_in;
 case state is
   when   "00" => newstate<= "0000";
   when   "01" => newstate <= "0100";
   when others => newstate <= "0100"; 
  end case;
End process;

-- transfer new state to old state
process (clk, newstate) 
  if rising_edge(clk) then
     oldstate <= newstate;
end process;

Finite state machine in VHDL

Truth table: logic

Register transfer

Library IEEE

  • Basic definitions for example:
  • More Libraries available
    Look for functions provided
    Speeds up development process
library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Test and input signals

  • Constant
  • Process label
  • Wait for statement

-- Clock period definitions
   constant clk_period : time := 0.02us; 
-- Clock process definitions
   clk_process :process
		clk <= '0';	wait for clk_period/2;
		clk <= '1';  wait for clk_period/2;
   end process;
    -- Stimulus process
   stim_proc: process
      -- hold reset state for 1us.
      wait for clk_period*50; -- 1us
      wait for clk_period*50; -- 1us
      A <= '0'; B <= '0';
      wait for clk_period*50; -- 1us
      A <= '0'; B <= ‚1';
    end process;

Input signal timing

procedure VECTORTIMING (CLKi,S1i,S0i: in std_logic) is
-- timing information for usage with synchronous designs and test
 constant TCYCLE : Time := 100ns;                      -- cycle time

    CLK <= CLKi after (TCYCLE/2), '0'after (TCYCLE);   -- CLK pulse width  
    S1 <= S1i   after 10ns, '0' after 70ns;
    S0 <= S0i   after 10ns, '0' after 70ns;
    wait for TCYCLE;                                   -- go to cycle end time 
end procedure VECTORTIMING;             

--     VECTORTIMING (CLKi,  S1i,  S0i );      
       VECTORTIMING ( '1',  '1',  '0‘ );

VHDL Design and Verification Environment

No cost
FPGA vendors: Altera, Xilinx
Xilinx WebPack free to download

Behavioral and structural VHDL


entity mod_m_counter is
      N: integer := 4;     -- number of bits
      M: integer := 10     -- mod-M
      clk, reset: in std_logic;
      max_tick: out std_logic;
      q: out std_logic_vector(N-1 downto 0)
end mod_m_counter;

architecture arch of mod_m_counter is
   signal r_reg: unsigned(N-1 downto 0);
   signal r_next: unsigned(N-1 downto 0);
   -- register
      if (reset='1') then
         r_reg <= (others=>'0');
      elsif (clk'event and clk='1') then
         r_reg <= r_next;
      end if;
   end process;
   -- next-state logic
   r_next <= (others=>'0') when r_reg=(M-1) else
             r_reg + 1;
   -- output logic
   q <= std_logic_vector(r_reg);
   max_tick <= '1' when r_reg=(M-1) else '0';
end arch;


entity LUT4_0DF0 is port( I0,I1,I2,I3: in STD_LOGIC;O: out STD_LOGIC);
end LUT4_0DF0;

architecture LUT4_0DF0_BODY of LUT4_0DF0 is
  component LUT20 port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
  component LUT2D port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
  component LUT2F port ( I0,I1 : in STD_LOGIC;O: out STD_LOGIC); end component;
  component MUX4 port(I0,I1,I2,I3,I4,I5 : in STD_LOGIC;O: out STD_LOGIC); end component;
  signal y1,y2,y3,y4,O2 : STD_LOGIC ;

  LUT2_1: LUT20 port map (I0,I1,Y1);
  LUT2_2: LUT2F port map (I0,I1,Y2);
  LUT2_3: LUT2D port map (I0,I1,Y3);
  LUT2_4: LUT20 port map (I0,I1,Y4);
  MUX0: MUX4 port map (Y1,Y2,Y3,Y4,I2,I3,O);
end LUT4_0DF0_BODY;
ISE Webpack can be used to transfer behavioral VHDL in structural VHDL.
AnalyzeJS.html transfers the structural VHDL to Electric compatible VHDL.
Electric can then synthesize the circuit with elements of circuit sclib.jelib.
An example is synthesis of a UART.

Summary VHDL

Next: 09 FPGA and Timing Closure