Hochschule Kempten      
Fakultät Elektrotechnik      
Microelectronics       Fachgebiet Elektronik, Prof. Vollrath      


11 Memory

Prof. Dr. Jörg Vollrath

Area, uP, Register, Scan cell

Video of lecture 11 (16.06.2021)

Länge: 1:10:08
0:3:45 Picture processing

0:8:0 Examples for memory applications

0:9:56 Memories in personal computers

0:11:30 Memory application

0:20:30 Memory Types

0:22:50 Word line, bit line memory array

0:25:25 Memory array

0:27:17 Memory SRAM LTSPICE schematic

0:30:40 6F2 DRAM manufacturing

0:40:0 SRAM manufacturing

0:49:30 SRAM schematic

0:55:0 Intel: Crosssection showing metal layers different thickness and width

0:56:0 REM picture of SRAM

0:57:20 Feature size and metal pitch

1:0:0 REM picture DRAM

1:2:13 Flash memory 2 TB SSD

1:13:10 Simulation memory operation

1:17:40 DDR3 SDRAM access

1:13:16 Overview remaining lectures, take home test

1:26:0 Typical exam problems




Picture Processing

Memories in personal computers

PC Memory

Memory: Application

HierarchyMemoryCost per Bit SpeedDensity
L1 CacheSRAM highest


32 kB; 128kB
L2 (L3) CacheSRAM 512 kB; 512kB (4MB)
Main MemoryDRAM 16 GB; 4..64 GB
Flash Memory (SD Card)NAND 4 GB; 16 GB..1 TB
Hard Disk MemoryMagnetic/Flash 4 TB/2..16 TB
Cache: Intel Celeron (Core) 2007; Intel Core i3-7300 (Kaby Lake, 2017, 14nm)

Memory Types

DRAM (capacitor)
SRAM (latch of transistors)
Flash (transistor with floating gate)
FRAM (Ferro Electric hysteresis)
MRAM (Resistance change due to magnetization)
PCRAM (resistance change due to solid/solid transition)
  • Word in bit
  • Memory capacty in bit (b) oder byte (B):
    k(ilo) =210 =1024, M(ega) = 220 =1048576, G(iga) = 230 , T(era)=240, P(eta)=250
  • Power consumption
  • Access time
  • Write time
  • Data Retention
  • Endurance

Needed Area

DRAM: 6F2 one capacitor + 1 select device: 1T + capacitor
SRAM: 256F2 4 transistors + 2 select devices: 6 T
Flash: 4F2 (16 level: 1F2) 1 Transistor with floating gate: 1T

Volatile versus nonvolatile memories

Information loss: Volatile versus nonvolatile memories
SRAM, DRAM lose information without power, Flash, EPROM and FRAM don’t.
DRAM loses information without constant refresh of memory cells.

Memory Array

  • Register (SRAM)
    Byte, Word, Double word

Memory array: large memory

  • ROM read only memory
  • RAM random access memory
    SRAM, static
    DRAM dynamic
  • NVM non volatile memory
    Flash Speicher

Memory Array

Lets analyze a typical DRAM from Micron, Samsung, Hynix.
Biggest size DRAM datasheet from Internet.
Number of outputs, row address, column address, banks.

DRAM Layout

DRAM Layout, cross section, 6F2

Top view:

Cross section:

Intel 14 nm SRAM cell

Top view:

Cross section:
Size: 140 x 364 nm2 = 10 x 26 F2 = 260 F2
FINFET: 8nm Width (draw 14 get 8), 42nm FIN pitch, gate pitch 70nm
Interconnect pitch 52nm
14nm Intel Core M Processore 1.3 billion Tr. 82 mm2 die size

Reference: Intel 14nm technology

Samsung 21nm 48L V- 256Gb NAND Flash memory in 2TB SSD

  • 7.4.2016 EE Times
  • 256 Gb Chip: 3 bit per cell
  • 512 GB K9DUB8S7M Component
    = 8*512 Gb -> 16*256Gb
  • 2 TB solid state drive (SSD)
  • 16 Chips (dies) 40um Thick
  • Die area: 100mm2
The density is not only determined by F, but by the number of bits ber cell(3) and vertical integration (48 layers of transistors, 16 dies)
Multiple bits per cell.
Multiple cells stacked vertically.
Multiple chips per package.
More functionality per volume.

Memory Array SRAM

Positive clock level control
CLK AND (A1, A0) selects a row
CLK AND (A2, A3) selects a column
WE AND CLK connects DI with data lines

Where is the memory cell with address (A3..A0) = "0110"?
Which switches are closed with address (A3..A0) = "0110"?
Memory cells are connected to BL and BLb.
BL and BLb are equalized with CLK='0'


Positive clock level control
Read 0000 '0', Read 0001, Write 0001 ‘1‘, Write 0100 ‘0‘, Read 0000 '0', Read 1110 '1', Read 1110 '1', Read 0100 '0', Read 0001 '1', Read 0000 '0', Read 0000 '0'
Delay 10ns from address until data appears


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
   generic(ADDR_RANGE: integer:=4;
           DATA_WIDTH: integer:=8);
   port (ADDRESS : in std_logic_vector(ADDR_RANGE-1 downto 0);
         DATA : out std_logic_vector(DATA_WIDTH-1 downto 0));
type ROM_TYPE is array (0 to 2**ADDR_RANGE -1) of std_logic_vector(DATA_WIDTH-1 downto 0);
constant ROM : ROM_TYPE :=
   DATA <= ROM(to_integer(unsigned((ADDRESS)));  -- Lesezugriff

VHDL-Code: RAM 01

entity Xilinx_one_port_ram_sync is
    ADDR_WIDTH: integer :=12;
    DATA_WIDTH: integer:=8
  port (
      clk: in std_logic;
      we: in std_logic;
      addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
      din: in std_logic_vector(DATA_WIDTH-1 downto 0);
      dout: out std_logic_vector(DATA_WIDTH-1 downto 0)
end Xilinx_one_port_ram_sync;

Ram_1K_by_16_0: entity Xilinx_one_port_ram_sync 
  generic map(ADDR_WIDTH=>10;DATA_WIDTH=>16)
  port map(clk => clk, we=>we,addr=>addr,din=>din,dout=>dout);

VHDL-Code: RAM 02

architecture Behavioral of Int_Memory is
  type ram_type is array (2**ADDR_WIDTH-1 downto 0) of
           std_logic_vector (DATA_WIDTH-1 downto 0);
  signal ram: ram_type:= (others => (others => '0')); 
  if ((clk‘event) and clk=‘1‘) then
     if (we =‘1‘) then
        ram(to_integer(unsigned(addr))) <= din;
     end if;
     dout <= ram(to_integer(unsigned(addr)));
  end if;
end process;
end Behavioral;


Cycle time:


  • Memory as data and program buffer
  • SRAM, DRAM, ROM, NAND flash memory
  • Capacity, (non)volatile, latency, bandwidth
  • Memory array: realization, layout, LTSPICE, VHDL
  • Memory access timing

Next: 12 Power, Clock, Input, Output (IO)