Overview
- Course setting
- Open access, content overview and web page
- LTSPICE schematics
- Electric design and layout
- UART example
- VHDL: behavioural to structural with Xilinx Webpack
- Standard cells for synthesis
- AnalyzeJS: Glue web tool
- Result
- Outlook
Generating structural VHDL with
Xilinx Webpack
and post processing with
AnalyzeJS.html
Synthesis of a UART with
Electric VLSI Design System
Simulation with LTSPICE.
Course setting
- Kempten, University of Applied Science
- Munich, Stuttgart area
- Master class: Microelectronics
- 15..30 international students
- 2 SWS (90 min) lecture, 2 SWS laboratory
- Language: English
- Semiconductor companies: Bosch, Infineon, Dialog
- Limited funding and manpower
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General Learning Outcome
General lessons Microelectronics provides
- Roadmap goal setting
- First any solution, then improvement
- Simulation before realization
- Automation avoiding mistakes and providing repeatability
- Working on a tight schedule
- Test, verification, root cause analysis and reflection
- How to deal with high volume and big data
Realize a chip in laboratory
Open access, content overview and web page
- Open access internet web page:
Immediate update and only one source
- Wep page HTML and JavaScript:
Equations, graphs, video, animation, buttons
Simulations, tools
Mobile devices, device independent
- Lecture content: From transistor to system
Books:
Harris,
Baker,
Holberg
- Laboratory:
Guided transistor and inverter performance
Open laboratory: Scan cell, synthesis, UART
- Tools:
Electric, LTSPICE, Xilinx Webpack, JavaScript
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LTSPICE schematic: Scan cell
- Filename: Scan_cell_small_CE
Subdirectory: LTSPICE
- Works directly with file
- Click and links
- Level of detail
- Symbols: sym
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<canvas id="Scan_cell_small_CE" width="300" height="250"
level="0" class="LTSPICE" sym="NAND2,TG,INVx,AND2,OR2"> </canvas>
A scan cell is used in this class to emphasize design for test.
This cell can be designed by hand or generated with the silicon compiler.
Electric design and layout
Java program using a portable Java
No cost
- Preferences
- Layout: Scale, Design Rules
- Schematic: Entry
- Simulation: LTSPICE
- Tools: Design rule check (DRC),
equivalence checking (LVS)
- Tool: Synthesis
- Tool: Compaction
- Libraries
- Test and Documentation
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Electric VLSI Design System
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Electric has most of the tools of a commercial software.
The results are not optimum, but the students learn what to expect from a
design software.
They also experience all the difficulties of engineering software, which
has no perfect user interface, but has to work somehow.
Scan cell example
- Silicon compiler generated layout from schematic
- Routing rules: M1 horizontal, M2 vertical
- Gaps between the cells
- Minimum transistor size
- Cell size more limited by connections than by transistors
UART example
Open Laboratory
- Transfer behavioural VHDL to structural VHDL: Xilinx Webpack Spartan 3
No cost tool and limited number of primitives
- AnalyzeJS.html tool: Mapping of 4 input LUTs to 2 input LUTs and multiplexer
AnalyzeJS.html
- Electric library for Spartan 3 primitives
sclib.jelib
- Synthesis result
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Step by step instructions:
UART synthesis
Cells for synthesis
Students designed 39 basic cells
Logic verification with simulation
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| FDP | LUT29 | LUT2E |
| MUXF5 | LUT2A | INV |
| FDCE | LUT2B | BUFGP |
| FDC | LUT2C | OBUF |
| FDC0 | LUT2D | IBUF |
| LUT21 | LUT2E | VCC |
| LUT22 | MUXD | GND |
| LUT23 | MUXL | LUT20 |
| LUT24 | MUX | LUT2F |
| LUT25 | MUXCY | MUX2L |
| LUT26 | XORCY | LUT2A |
| LUT27 | MUX4 | MUX4L |
| LUT28 | MUX2 | MUX2D |
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These cells are necessary to realize all possible 2 input truth tables (16)
and to realize the Spartan 3 FPGA primitives..
AnalyzeJS.html
Glue script between Xilinx Webpack
and Electric for VHDL
- STD_LOGIC to BIT
- STD_VECTOR to single lines
- LUT3 and LUT4 to LUT2 and MUX
- Example and test embedded
- Copy and paste of text
- List of cells
- Components VHDL code
- Entities for LUT3 and LUT4
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AnalyzeJS.html
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The script is realized using JavaScript and accessable from the internet.
Using node.js it can also be employed in a regular tool chain.
Synthesis Result Layout
Synthesis took 2..3 minutes.
Area: 14554 x 7938 F
2; 10 rows;
Synthesis design rules: 4, 3, 32, 8, -9
Tools: DRC: Check Hierarchically: cells ok
uart_test takes a long time.
Outlook
Summary:
- Open access documentation and laboratory successfull
- LTSPICE can be easily documented and shared
- No cost VHDL synthesis successfull
- Sucessfull web tool for VHDL translation implemented
- Web tools and pages are easily maintainable and accessable
- All tools are also working locally from file system
- It is very easy to update a web page
Outlook:
- Improvement of LTSPICE display
- Web layout display and generation tool
- Routing with more than 2 layers metal
- Routing in a chip frame
- Improvement of documentation
- IRSIM simulation
- Chip fabrication