Outline

• Motivation and Objectives
• Learn typical steps of a chip design
• Experience an EDA tool chain flow
• Implement a simple function
• Simulate a simple function (Vivado/Verilog, LTSPICE)
• Analyze synthesis results: number of transistors and simulation
• Verilog project and files
• Interface
  Input: CLK, CE, RST
  Test Interface: Input: TE, TDI Output: TDO
  Input: a[3:0] Output: y[3:0]
• Simulation
• BASYS3 FPGA Board Implementation
• Chip Design flow
  Verilog, VHDL, AnalyzeJSV, Electric, Layout, Padframe
  (Tiny Tape out)
• Deliverables

Verilog Project Files

Verilog Interface

module SerialCompute( clk, ce, rst, te, tdi, tdo, a,y); input clk; input ce; input rst; input te; input tdi; input [3:0] a; output tdo; output [3:0] y;

Verilog Design Top Module

 wire tdo1;
 wire tdo2;
 wire [3:0] ay0;
 wire [3:0] ay1;
 
  parSer pS0(.clk(clk), .ce(ce), .rst(rst), 
                    .te(te), .tdi(tdi), .tdo(tdo1), 
                    .a(a), .y(ay0)); 
  serPar sP0(.clk(clk), .ce(ce), .rst(rst), 
                    .te(te), .tdi(tdi), .tdo(tdo), 
                    .a(ay1), .y(y)); 

  serInvSer sIS0(.clk(clk), .ce(ce), .rst(rst), 
                    .te(te), .tdi(tdi), .tdo(tdo2), 
                    .a(ay0), .y(ay1)); 

Verilog Simulation Top Module Instances

module Test1_SerialCompute();
 reg clk = 1;
 reg ce = 1;
 reg rst = 0;
 reg te = 0;
 reg tdi = 0;
 reg [3:0] a = 4'b1111;

 wire [3:0] y5;
 wire tdo5;

 SerialCompute sC0(.clk(clk), .ce(ce), .rst(rst), 
                    .te(te), .tdi(tdi), .tdo(tdo5), 
                    .a(a), .y(y5)); 

Verilog Simulation Top Module Vectors(2)

// Clock process definitions
always #10 clk = ~clk;  // setup Tclk = 20ns 50 MHz CLK
initial begin
  #0 a = 4'b1111; 
  #15 rst = 1;         // reset
  #10 rst = 0;         //
  #20 te = 1;          // configure via te
      tdi = 0;         // test data 0
  #20 tdi = 0;         // test data 1
  #20 tdi = 0;         // test data 2
  #20 tdi = 0;         // test data 3
  #20 te = 0;
  #5  te = 0;
  
  #20 a = 4'b0111;     // start a data in
  #20 a = 4'b1011;
  #20 a = 4'b0101;
  #20 a = 4'b1100;
  ...

Verilog Simulation Result

Synthesis and Layout

• Run Synthesis
• Open design
• write structural VHDL to file
  write_vhdl <filename>
  write_vhdl C:/temp/2025_Micro_JV/SerialCompute.vhd
• Open the .vhd file in an Texteditor
• Open the web page AnalyzeJSV.html
• Paste the contents of the .vhd file into the text box
• Push 1. Process VHDL for Electric (Type: BIT)
  Hopefully the VHDL is translated for Electric VLSI Design System
• Open Electric VLSI Design system and load sclib.jelib
• Copy the resulting VHDL from the web page in section 'Processed output' into a new cell {VHDL} in Electric VLSI Design system
• Run Tools, Silicon Compiler, Convert Current Cell to Layout
  If errors occur refer to the 08 Systems and VHDL microelectronics lecture.
• Add a LTSPICE simulation stimulus to the layout and start LTSPICE simulation.

Direct Newton iteration for .op point skipped.
Gmin stepping method for .op point skipped.
Starting source stepping with srcstepmethod=0

Generating LTSPICE input signals

• TestJS.html can be used to generate LTSPICE input signals
• In the input text field put your vectors
  Example of 3 vectors for clk, 8 input signals and 5 expected signals:
  

  	ce,rst,te,tdi,a__3,a__2,a__1,a__0;xtdo,xy3,xy2,xy1,xy0;COMMENT
      1,0,0,0,1,1,1,1;0,0,0,0,0;
      1,1,0,0,1,1,1,1;0,0,0,0,0;
      1,0,0,0,1,1,1,1;0,0,0,0,0;
      

• The section 'LTSPICE Code' has the PWL voltage sources for these vectors.
  

       VCLK CLK 0 PULSE(0 1 1e-8 1n 1n 9e-9 10n)
       Vce ce 0 PWL( 1.0000e-10 1
       + 1.0000e-8 1 1.0100e-8 1 2.0000e-8 1 2.0100e-8 1 3.0000e-8 1 3.0100e-8 1 4.0000e-8 1 4.0100e-8 1 5.0000e-8 1 5.0100e-8 1 6.0000e-8 1
  	 ...
  	

• LTSPICE simulation should match Vivado simulation

.include cmosedu_models.txt
.options noopiter srcstepmethod=0 gminsteps=0
VCLK clk 0 PULSE(0 1 9n 1n 1n 9n 20n)
VCE ce 0 DC 1
vdd vdd 0 DC 1
Vddx vddx 0 DC 1
VGND gnd 0 DC 0
VGNDx gndx 0 DC 0
Vrst rst 0 PULSE(0 1 14n 1n 1n 9n 600n)
Vtdi tdi 0 DC 1
Vte te 0 PULSE(0 1 44n 1n 1n 80n 600n)
* output y__0 y__1 y__2 y__3 tdo
.tran 0 1000n

Tasks

• Compare LTSPICE simulation and Vivado simulation for SerSimple.v (serPar or parSer)
• Are there errors during synthesis process and can these be fixed?
• What is the optimum number of rows to get a square layout area?
  Document the layout
• What is the area per transistor in this design and in the subcircuits?
• What is the LTSPICE runtime simduration (error log Total elapsed time:) for which number of transistors and which simlength (.tran command)?
• What is the delay from CLK/input/output for different circuits (table below)?
  Can you simulate and extract delay times with 'conservative RC' estimations?
• Generate a simulation pattern in Verilog (Vivado) and for LTSPICE for different serial or parallel inputs (table below).
• Is there a maximum number of transistor for LTSPICE simulation?
• Can serInvSer.v be used to implement as starting point for other functions for a stream?
• 2 page final report in IEEE format due 6.7.2025

Open Tasks and Issues

• Prepare BASYS3 implementation
  switches, LEDs, buttons and configuration
• Generate Pad frame