Microelectronics

03 MOSFET

Prof. Dr. Jörg Vollrath

02 History

Video of lecture 03 MOSFET, SPICE models, propagation delay 31.03.2021

Länge: 01:26:05

0:0:0 0

0:3:9 Goals today

0:6:36 Output and transfer curve

0:9:48 50 nm technology voltage limit

0:14:58 Subthreshold characteristic

0:16:49 Bulk source voltage and threshold voltage

0:19:25 Design by selecting W or number of unit transistors

0:24:29 MOSFET typical layout and rules

0:30:37 SPICE models 1 um, 50 nm

0:35:39 Infineon 130 nm MOSFET transistor parameters

0:40:29 SPICE models details

0:48:31 MOSFET as switch

0:50:39 Transistor RC model

0:52:39 Transistor Capacitances

0:59:19 Propagation delay

1:1:39 Rising and falling output

1:8:49 equivalent capacitance, Miller capacitance

1:16:49 Timing closure

Overview

Moores Law
Microelectronic products, complexity, hierarchy
Technologies: ASIC, FPGA, Microcontroller
You have a basic understanding of a MOSFET

Gate, Source, Drain, Bulk/Well: VGS, VDS, VBS
Threshold voltage Vth, Drain source current IDS
Transfer and output IV curve
Output resistance RDSon
Layout: Width, Length
Capacitance and RDSon,C delay

Microelectronic products

Computer			mobile phone
Consumer		Automotive		Industrial

Hierarchical Description

Top Down

System

Subsystem_i, Subsystem_j

Subsystem_k, Subsystem_l

Bottom up

Find one solution and then optimize

Citations

Optimization

“The First Rule of Program Optimization: Don't do it.
The Second Rule of Program Optimization (for experts only!): Don't do it yet.”
- Michael A. Jackson

Find a solution first

Diagnose problems

“We should forget about small efficiencies, say about 97% of the time:
premature optimization is the root of all evil.
Yet we should not pass up our opportunities in that critical 3%.
A good programmer will not be lulled into complacency by such reasoning,
he will be wise to look carefully at the critical code;
but only after that code has been identified”
- Donald Knuth

Identify the problem through test first

Design Flow

Technologies

Comparison	ASIC	FPGA	Microcontroller
Target market	High volume	Prototype to medium volume	Single to high volume
Design speed	Slow	Fast	Faster
Design Tools	Expensive	No cost	No cost
Efficiency	Optimum	slow clock, parallel operation	slow clock, seriell operation, analog function

ASIC: Application specific integrated circuit.
FPGA: File programmable gate array.

Systems (1)

Raspberry Pi: µC, periphery Operating system: Linux Communication: Wifi, Webserver C(++), JavaScript Application: C(++), JavaScript
Arduino: Microcontroller (µC) No operating system Application and Communication C

Matlab, Labview can support some platforms.

Systems (2)

Zedboard: FPGA, µC Field programmable gate array (FPGA) FPGA programming: VHDL, Verilog, IP Wizard Optional operating system: Linux Communication: Wifi, Webserver C(++), JavaScript Application: C(++), JavaScript	Switch matrix, logic and registers, programmable
ASIC Proprietory software for design Electronic design automation (EDA) software tools: linux, perl, phyton, JavaScript	Full custom ASIC Standard cell ASIC Gate Array Based Asic Foundries: TSMC, UMC Educational: MOSIS Europractice Zero To ASIC

Matlab, Labview can support some platforms.

Microelectronics

Bottom up

MOSFET transistors, performance, layout and standard cells

NAND, AOI logic, scan flip flop

Place and route with VHDL

Make a chip with IOs, circuit and test structures

Electronic system

System Description

State diagram, truth table
Schematic (Graphic with symbols)
Logic diagram
Signal behaviour
Hardware description language (HDL): Verilog, VHDL
SystemC, Matlab, Simulink, Labview
Programming Language: JavaScript

Modelling
Simulation

Structural Description
Behavioral Description

Analog and digital signals

MOSFET Transistor

Equations:

Technology versus electrical properties
Electrical properties for circuit simulation (SPICE program)

4 Terminal device

Gate, source, drain, bulk (well)
Voltage: V_GS gate source voltage, V_DS drain source voltage, V_BS bulk source voltage
Current: Gate, Drain source, bulk or substrate

Electrical Characteristics

Transfer Curve:

lin I_DS versus V_GS -> shows threshold voltage
log I_DS versus V_GS -> shows weak inversion and off current

Output Curve: I_DS versus V_DS with various V_GS -> shows output conductance

Technology versus Electrical Characteristics: Roll of curve -> V_th versus L_eff

Transistor Evolution

How much area uses one transistor?
Theoretical minimum:
Active area: W*L*4
Contacts: W*L*4*3
Minimum Feature size F
A=16*F²
Example:
F = 45 nm; 731M Transistors; 262 mm²
A = 262 mm²/(731*106)= 358413 nm² = 177*F²

Courtesy of Intel
2008 Intel Core i7
731 Million MOS Transistors
45 nm process
263 mm²
2.6..3.2 GHz

Summary Transistor Evolution

MOSFET- transistor
Moore‘s law
Implications of reduced feature size:
30% Productivity gain per year
Power consumption, complexity/features, price
Hierarchical Design
Verification

Microelectronics deals with small electronic components
Transistor, diode, resistor, capacitor, inductance
Microelectronic systems are getting cheaper
Complex systems can be realized
Functions are getting cheaper

Typical microelectronic components of interest are:
Microcontroller (Microprocessor, memory, digital and analog functions)
FPGA (Field programmable gate arrays)
ASIC (Application specific integrated circuits)
This class shows how to design digital and analog CMOS microelectronic components and systems

Inverter schematic and layout

Schematic and layout are representing an inverter.
An inverter uses a NMOSFET and a PMOSFET.
The schematic shows the components and connections.
The layout has added different colors for different layers of the manufacturing process and each component.
These colors are transferred into the schematic showing the relationship between layout and schematic.
Wiring and transistor gates and diffusion have a minimum physical size of width and length of F.
There are also minimum distances required to prevent shorts.

It is difficult to automatically transform one view into the other.
A schematic is drawn to be able to easily understand the circuit. On the left is GND, on the right VDD, on the top inputs, on the bottom outputs.
In a schematic connection between 2 pins can be accomplished by labeling the pins with the same names. Lines can cross without resulting in short circuits.
A layout is drawn for symmetric and regular patterns, avoiding signal cross coupling and shape distortion, and having minimum size.

Equations of a n-channel MOSFET

$I_{DS}= \cases{ \begin{matrix} 0 & \text{for} & V_{GS} \leq V_{th} & \text{Off} \\ I_{on} exp^{\frac{ V_{GS}-V_{th} - \frac{kT}{e}}{\frac{kT}{e}}} \left( 1+\lambda V_{DS} \right) & \text{for} & 0 \leq V_{GS} - V_{th} \lt \frac{kT}{e} & \text{Weak inversion} \\ \beta \left( V_{GS}-V_{th} \right)^2 \left( 1+\lambda V_{DS} \right) & \text{für} & \frac{kT}{e} \leq V_{GS} - V_{th} \lt V_{DS} & \text{Saturation} \\ \beta \left( 2 \left( V_{GS}-V_{th} \right) V_{DS} - V_{DS}^2 \right) & \text{for} & \frac{kT}{e} \leq V_{GS} - V_{th} \geq V_{DS} & \text{Linear} \end{matrix} }$

$\beta = \frac{\mu_n \epsilon_{ox}}{2d_{ox}} \frac{W}{L} = \frac{1}{2} \mu_n C_{ox}^{'} \frac{W}{L} = \frac{1}{2} K_{n}^{'} \frac{W}{L} = \frac{1}{2} K_{n}$

Quelle Vollrath

Draw a IDS(VGS) and IDS(VDS) curve with Vth = 1V (0.3V), Kn = 100 µAV^-2 and λ = 0.02 V^-1

V_th threshold voltage
λ Output conductance
W width, L length
µ mobility
C_ox = e /d_ox Gate oxide capacitance
V_t = kT/q (300K) = 0.0259 V

Simulation verifies first correct V_th and maximum current I_DS at maximum voltage V_dd.
Then the input capacitance C_ox is confirmed with AC simulation of a RC circuit having the MOSFET gate as capacitance C.

Microelectronic has only transistors as elements.
Design is done using transistors with choosing W and L.
MOS transistors are also used as capacitances, resistors, diodes and lateral bipolar transistors.
In sub 50nm processes FINFETs are used having a fixed L and W. These transistors are called unit transistors. Circuits are designed combining transistors in series or parallel to get the desired W/L ratio. This makes automated design easier.

Elektronik 3, 08 MOSFET

NFET Transistor subthreshold characteristic

NFET.asc

Version 4
SHEET 1 880 680
WIRE 352 48 272 48
WIRE 272 80 272 48
WIRE 336 128 272 128
WIRE 224 160 160 160
WIRE 336 176 336 128
WIRE 336 176 272 176
WIRE 336 192 336 176
FLAG 336 192 0
FLAG 160 160 A
IOPIN 160 160 In
FLAG 352 48 VDD
SYMBOL nmos4 224 80 R0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=0.05u w=0.1u
TEXT 96 -88 Left 2 !.include cmosedu_models.txt\nVDD VDD 0 DC 1\nVA A 0 DC 1
TEXT 96 8 Left 2 !.dc VA 0 1 0.01 VDD 0.1 1 0.9

MOSFET transistors can also be operated in the subthreshold region for low voltage power supply.
The graph shows an increase in current by a factor of 10 for 100 mV change in V_GS.

Threshold voltage V_th

$V_{th}= V_{th0} + \left( \gamma \sqrt{V_{SB}+2\phi_F}-\sqrt{2\phi_F}\right)$

V_th: Threshold voltage
V_SB: Source-bulk voltage
$\phi_F$ : Fermipotential of semiconductor
$\gamma$ : Body factor

Graph:

$V_{th0}=1V$
$\phi_{F}=0.3V$
$\gamma=0.75 \sqrt{V}$

MOSFET Transistor design

Choosing W and L for I_DS

L is fixed to minimum feature size
W can be changed
Unit transistors have a fixed W and L
Circuits are using unit transistors in parallel and series

Threshold voltage V_th

V_th is fixed for a given process
V_th can change with:
oxide thickness, doping, length and width
Modern processes have different devices:
High V_th, low V_th, thick and thin oxide devices

Process sensitivity analysis: Process window lot (PWL)
Check in simulation different V_th and W L variations

MOSFET layout

Simple: crossing of polysilicon and contact diffusion
Modern processes use unit transistors
Finger structure
Serpentine
Common centroid layout

sclib.jelib: UNITExample{lay}, UNITLong{lay}

MOSFET SPICE models

Long channel MOSFET F = 1 µm, VDD = 5 V
Parameter	NMOS	PMOS	Comment
V_Th	0.8 V	0.9 V	Typical
KP	120 µA/V²	40 µA/V²	d_ox = 20 nm
C'_ox	1.75 fF/µm²	1.75 fF/µm²	C_ox = C'ox W L
λ	0.01 V^-1	0.0125 V^-1	L = 2
R	15 kΩ L/W	45 kΩ L/W
Short channel MOSFET F = 50 nm, VDD = 1 V
Parameter	NMOS	PMOS	Comment
V_Th	0.28 V	0.28 V	Typical
KP	60 µA/V²	30 µA/V²	d_ox = 1.4 nm
C'_ox	25 fF/µm²	25 fF/µm²	C_ox = C'ox WL
λ	0.6 V^-1	0.3 V^-1	L = 2
R	34 kΩ/W	68 kΩ/W

Table according to Baker. Width W and L length are applied in multiples of feature size F for KP.

Propagation delay can be calculated with t_PD = 0.7 · R · C
R is the resistance of NFET or PFET. C is the sum of the output capacitance (C_oxn) and input capacitance (3/2 C_ox).
C = (3/2 + 1 ) (C_oxn + C_oxp)

A 1 µm unit transistor has a C_ox of 1.75 fF/µm² and R of 15 kΩ (45 kΩ).
t_PD = 0.7 · 2 · 1.75 fF · 0.5 · ( 15 kΩ + 45 kΩ) = 73.5 ps

A 50 nm unit transistor has a C_ox of 25 fF/µm² · 50nm · 50 nm = 62.5 aF and R of 34 kΩ (68 kΩ).
t_PD = 0.7 · 2 · 25 fF/µm² · 50 nm · 50 nm · 0.5 · ( 34 kΩ + 68 kΩ) = 2.23 ps

Simulated inverter 24..32 ps

More models:

Baker: 1 µm MOSFET model, 50 nm MOSFET model, cmosedu_models.txt
Sedra Smith Level=1 5 µm, 0.5 µm: sedra_lib.lib
Allen, Holberg Level=3 0.8 µm: Holberg.txt
TSMC 0.25um CMOS MOSFETs (level 3) t14y_tsmc_025_level3.lib from MOSIS .
TSMC 0.18um CMOS MOSFETs (level 3) t92y_mm_non_epi_thk_mtl-params_TSMC_018.txt from MOSIS .
180nm CMOS Model
130nm CMOS Model
Archived PTM CMOS models 7nm, 10nm, 14nm, 16nm, 20nm, 22nm, 32nm, 45nm, 65nm, 90nm, 130nm, 180nm

CD4007

.model CD4007N NMOS(LEVEL=1 KP=500u VT0=1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)
.model CD4007P PMOS(LEVEL=1 KP=500u VT0=-1 LAMBDA=0.002 CGSO=45n CGBO=2n CGDO=45n)

ALD1106, ALD1107

.model ALD1106N NMOS(LEVEL=1 KP=0.48m VT0=0.7 LAMBDA=0.018 CGDO=100n CGSO=100n)
.model ALD1107P PMOS(LEVEL=1 KP=0.2m VT0=-0.7 LAMBDA=0.018 CGDO=100n CGSO=100n)

130 nm Infineon MOSFET transistors

Infineon 130 nm platform

2022 03 22 04 MOSFET Microelectronics Prof. Dr. Joerg Vollrath

Microelectronics

03 MOSFET

Prof. Dr. Jörg Vollrath

Video of lecture 03 MOSFET, SPICE models, propagation delay 31.03.2021

Overview

Microelectronic products

Consumer

Automotive

Industrial

Hierarchical Description

Find one solution and then optimize

Citations

Optimization

Find a solution first

Diagnose problems

Identify the problem through test first

Design Flow

Technologies

ASIC

FPGA

Microcontroller

Systems (1)

Raspberry Pi: µC, periphery

Arduino: Microcontroller (µC)

Systems (2)

Zedboard: FPGA, µC

ASIC

Microelectronics

Bottom up

MOSFET transistors, performance, layout and standard cells

NAND, AOI logic, scan flip flop

Place and route with VHDL

Make a chip with IOs, circuit and test structures

Electronic system

System Description

Analog and digital signals

MOSFET Transistor

Transistor Evolution

Summary Transistor Evolution

Inverter schematic and layout

Equations of a n-channel MOSFET

Draw a IDS(VGS) and IDS(VDS) curve with Vth = 1V (0.3V), Kn = 100 µAV-2 and λ = 0.02 V-1

NFET Transistor subthreshold characteristic

Threshold voltage Vth

MOSFET Transistor design

MOSFET layout

MOSFET SPICE models

CD4007

ALD1106, ALD1107

130 nm Infineon MOSFET transistors

Next

Draw a IDS(VGS) and IDS(VDS) curve with Vth = 1V (0.3V), Kn = 100 µAV^-2 and λ = 0.02 V^-1

Threshold voltage V_th