Interface Electronics12 Sigma Delta Oversampling ADCProf. Dr. Jörg Vollrath11 Pipeline ADC |
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0:0:0 Oversampling ADC 0:4:36 Sigma Delta ADC Architecture 0:12:38 First order passive Sigma Delta Modulator 0:16:51 Internal voltage calculation 0:17:10 0 0:17:10 Example Sigma Delta 0:19:46 Transfer function 0:22:10 f3dB = 15.9 kHz 0:25:46 Output data sequence 0:29:16 dt/R/C = 0.05 0:33:6 Time sequence of voltages 0:36:6 High level simulator (webpage) 0:42:12 LTSPICE simulation sine 0:48:4 General signal and noise transfer function 0:51:14 Noise Shaping 0:52:48 Digital filter and decimator 0:56:16 Example simulation ramp 1:0:46 Example simulation sine 1:5:46 Discussion understanding and simulation 1:9:21 Increasing Signal to noise with oversampling |
Nyquist ADCOversamplingfCLK = OSR · 2 · fbw Clock frequency is much higher than bandwidth. Pulse count Modulation (PCM)Predictive CodingQuantize difference of the signal Sigma delta converter |
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Internal voltage levels:The voltage V(INT n+1) at clock cycle n+1 is:\( V_{int n+1} = V_{int n} + \frac{\delta t}{C} \left( \frac{ V_{not(Dout)} - V_{int n}}{R} + \frac{V_{in} - V_{int n}}{R} \right) \) \( V_{int n+1} = V_{int n} + \frac{\delta t}{C \cdot R} \left( V_{not(Dout)} + V_{in} - 2 \cdot V_{int n} \right) \) \( \delta t \) is the period of the clock. \( V_{Dout} \) in a real logic circuit is 0V or VDD. \( \frac{\delta t}{C \cdot R} = \frac{2 \pi f_{sample}}{f_{CLK}} = \frac{2 \pi }{OSR} \) These equations are used for a high level simulation. High level simulation: 1st order sigma delta simulation Since Vint has to stay between 0V and VDD: \( \frac{\delta t}{C \cdot R} 2 V_{DD} \lt V_{DD} \) \( C \cdot R \gt \frac{2}{f_{sample} } \) \( \frac{1}{C \cdot R} \lt \frac{f_{sample} }{2} \) The bandwidth limit of RC has to be smaller than fsample/2. The bandwidth limit of RC has to be greater than the interested bandwith. fsample/2/OSR \( 2 \pi f_{bw} \lt \frac{1}{C \cdot R} \lt \frac{f_{sample} }{2} \) |
t [µs] | 0 | 1 | 2 | 3 | 4 |
vin | 0.3V | ||||
vint | 0.5V | ||||
vout | 0V |
t [µs] | 0 | 1 | 2 | 3 | 4 |
vin | 0.3V | 0.3V | 0.3V | 0.3V | 0.3V |
vint | 0.5V | 0.515V | 0.479V | 0.496V | 0.511V |
vout | 0V | 1V | 0V | 0V | 1V |
Signal pole: ω=3/(RC) Noise zero: ω=2/(RC) Noise pole: ω=3/(RC) Position fclk Position fbw = 3/(2 π R C) Noise is digitally filtered. \( \epsilon_q = \frac{LSB}{\sqrt{12}} \) \( - 20 log \sqrt{12} = -10.8 dB \) |
SINC Filter Filter order: SINC, SINC2, SINC3 The order of the filter has to be one more than the sigma delta modulator to realize the full signal to noise benefit. |
![]() A decimating Sinc2 filter has the following schematic with 2 integrators and 2 differentiators: ![]() |
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Example: fbw = 1 kHz 1. Order 1-bit sigma delta 8-bit resolution desired. |
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Example: 8-bit signal with 4-bit noise amplitude. Signal: \( V_{rms} = \frac{V_{amplitude}}{\sqrt{2}} \) Noise: Vrms = VPP/6 = Vamplitude/3
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