Interface Electronics 12 Sigma Delta Oversampling ADC Prof. Dr. Jörg Vollrath 11 Pipeline ADC

Review and Overview

Review:
Overview:

• Various ADC architectures
• Data converter systems:
  Nyquist rate, oversampling, undersampling
• Objectives sigma delta converter
• Oversampling, filter, aliasing, speed and resolution
• History of oversampling
• Sigma Delta converter architecture
• Passive 1st order sigma delta converter: schematic
• Passive 1st order sigma delta converter: SPICE
• Passive 1st order sigma delta converter: signal example
• Passive 1st order sigma delta converter: RC and filter

History

Nyquist ADC Oversampling fCLK = OSR · 2 · fbw Clock frequency is much higher than bandwidth. Pulse count Modulation (PCM) Predictive Coding Quantize difference of the signal Sigma delta converter

Sigma Delta ADC Architectures

1st order passive Sigma Delta Converters 2nd order active Sigma Delta Converters Higher order active Sigma Delta Converters Mashed Sigma Delta Converters Signal to noise ratio Transfer function and stability Voltage range preventing saturation Digital signal processing: filter, decimation

Questions

How to build a sigma delta ADC?

• Literature, Theory:
  Baker, Razavi, Holberg, Wikipedia, SSCC
• LTSPICE simulation
• Digital filter
  
• Need for high level simulation
• Realization, Measurement
• Review, Comparison

Overview

• Internal voltages: LTSPICE, high level simulation
• Transfer function: Stability and noise shaping (SNR)
• Signal to noise ratio and architectures
  First order, second order, higher order
• Digital filters
  Digital time domain circuits and frequency representation
  Realization
• Example realization
  Passive
  Active: continous time realization (CT)
  Cascaded (MASH)
  Active: switched capacitor realization (SC)
CIFB architecture

First order passive Sigma Delta Modulator

Internal voltage levels: The voltage V(INT n+1) at clock cycle n+1 is: \( V_{int n+1} = V_{int n} + \frac{\delta t}{C} \left( \frac{ V_{not(Dout)} - V_{int n}}{R} + \frac{V_{in} - V_{int n}}{R} \right) \) \( V_{int n+1} = V_{int n} + \frac{\delta t}{C \cdot R} \left( V_{not(Dout)} + V_{in} - 2 \cdot V_{int n} \right) \) \( \delta t \) is the period of the clock. \( V_{Dout} \) in a real logic circuit is 0V or VDD. These equations are used for a high level simulation. High level simulation: 1st order sigma delta simulation Since Vint has to stay between 0V and VDD: \( \frac{\delta t}{C \cdot R} 2 V_{DD} \lt V_{DD} \) \( C \cdot R \gt \frac{2}{f_{sample} } \) \( \frac{1}{C \cdot R} \lt \frac{f_{sample} }{2} \) The bandwidth limit of RC has to be smaller than fsample/2. The bandwidth limit of RC has to be greater than the interested bandwith. fsample/2/OSR \( 2 \pi f_{bw} \lt \frac{1}{C \cdot R} \lt \frac{f_{sample} }{2} \)

Example: First order passive Sigma Delta Modulator

The circuit with R = 1 kΩ, C= 20 nF is operated with V_DD = 1 V, V_CMP = 0.5 V and f_S = 1 MHz.
What is the maximum allowed input voltage?
What is the cut-off frequency of the RC input low pass?
Calculate vout(t) for 4µs if vin=0.3V. The starting value for vint=VCM and vout=0V. Assume a constant current through R for a sampling cycle.

1st order passive Sigma Delta high level simulation

High level simulation: 1st order sigma delta simulation

• Internal voltage simulation: Verification of result from previous calculation
• Ramp test: Dead zones and noisy transition
• Digital filter realisation: Averaging, SINC, droop, bitwidth
• FFT: Signal to noise improvement with OSR and filter

General signal and noise transfer function

A first order sigma delta analog digital converter.

\( V_{out}(f) = V_{in}(f) \frac{A(f)}{1 + B(f) A(f)} + E(f) \frac{1}{1 + B(f) A(f)} \)

\( V_{out}(f) = V_{in}(f) \frac{1}{B(f) + \frac{1}{A(f)}} + E(f) \frac{1}{1 + B(f) A(f)} \)

There is a signal transfer function and a noise transfer function.

First order passive Sigma Delta Modulator signal and noise transfer function

\( \frac{v_{in} - v_{int}}{R} + \frac{-v_{out} - v_{int}}{R} = i_{int} \)
\( v_{in} - v_{int} - v_{out} - v_{int} = i_{int} R \)
\( v_{in} - v_{out} - 2 \cdot v_{int} = i_{int} R \)
\( v_{in} - v_{out} = i_{int} R + 2 \cdot v_{int}\)
\( i_{int} = v_{int} j \omega C \)
\( v_{int} = \frac{v_{in}-v_{out}}{j \omega C R + 2} \)
v_int = A(f) · (v_in - B(f) v_out)
\( B(f) = 1 \)      \( A(f) = \frac{1}{j \omega C R + 2} \)
\( V_{out}(f) = \frac{V_{in}}{C R} \frac{1}{j \omega + \frac{3}{R C}} + E(f) \frac{j \omega + \frac{2}{R C}}{j \omega + \frac{3}{R C}} \)

Noise shaping

Signal pole: ω=3/(RC) Noise zero: ω=2/(RC) Noise pole: ω=3/(RC) Position fclk Position fbw = 3/(2 π R C) Noise is digitally filtered. \( \epsilon_q = \frac{LSB}{\sqrt{12}} \) \( - 20 log \sqrt{12} = -10.8 dB \)

Digital filter and decimator

SINC Filter Filter order: SINC, SINC2, SINC3 The order of the filter has to be one more than the sigma delta modulator to realize the full signal to noise benefit.

A decimating Sinc2 filter has the following schematic with 2 integrators and 2 differentiators:

Calculating Signal to noise ratio

\( V_{noise,RMS}^{2} = 2 \int_0^{BW}{|NTF(f)|^2|V_{Qe}(f)|^2} df \)
Quantization noise spectral density divides the quantization error with sampling frequency:
\( |V_{Qe}(f)|^2 = \frac{V_{LSB}^{2}}{12 f_{sample}} \)
Transfer function:
\( V_{out}(f) = STF(f) v_{in} + NTF(f) V_{Qe}\)
First order passive modulator :
\( V_{out}(f) = \frac{V_{in}}{C R} \frac{1}{j \omega + \frac{3}{R C}} + \frac{E(f)}{R C} \frac{j \omega R C + 2}{j \omega + \frac{3}{R C}} \)
Since signal transfer function and noise transfer function have the part:
\( STF(f) = \frac{1}{j \omega + \frac{3}{RC}} \)
This cancels out for signal to noise ratio.

Calculating Signal to noise ratio (continued)

\( V_{noise,RMS}^{2} = 2 \frac{V_{LSB}^{2}}{12 f_{sample}} \int_0^{BW}{(2 \pi f R C + 2)^2} df \)
\( V_{noise,RMS}^{2} = 2 \frac{V_{LSB}^{2}}{12 f_{sample}} \left( {(2 \pi R C )^2} \frac{BW^3}{3} + 4 \pi R C \frac{BW^2}{2} + 4 BW \right) \)
Sinc-shaped lowpass filter:
\( BW = \frac{f_{sample}}{2 OSR} \)

First part only: \( V_{noise,RMS}^{2} = \frac{V_{LSB}^{2}}{12 } {(2 \pi R C)^2} \frac{f_{sample}^2}{12 OSR^{3}} \)

\( SNR = 20 log\frac{V_{signal,rms}}{V_{noise, rms}} \)
\( SNR = 6.02 N + 1.76 - 20 log \frac{(2 \pi R C) f_{sample}}{\sqrt{12}} + 20 log OSR^{\frac{3}{2}} \)

\( SNR = 6.02 N + 1.76 - 20 log \frac{(2 \pi R C) f_{sample}}{\sqrt{12}} + 30 log OSR \)
With no oversampling signal to noise ratio decreases by:
\( d SNR = - 20 log \frac{(2 \pi R C ) f_{sample}}{\sqrt{12}} \)
The maximum value for f_RC = 1 / (2 π R C) = 0.5 f _sample
. \( d SNR = -20 log(\frac{2}{\sqrt{12}}) = 4.77 dB \) With larger oversampling rates signal to noise ratio improves by 30 log 2 = 9 dB, 9 dB / 6 dB = 1.5 bits for doubling OSR.

Increasing signal to noise with oversampling