Laboratory 4: Measuring a 10 Bit C2C DAC

Components:


1 x Breadboard
22 x Capacitors (10 pF, 100 pF, 1 nF)
Amplifier and sample and hold:
1 x LF398
1 x LM324
1 x ALD1106
1 x ALD1107
2 x Resistors 100 kΩ
Easy wiring:
5 x 12 Pin connectors

Task:


There will be 3 parts:

  1. Characterize measurement equipment.
  2. Measure static and dynamic performance of a C2C-DAC.
    Experience measurement problems and learn how to improve INL and DNL by circuit adjustments and digital assistance.
  3. Use an opamp and a sample and hold

This is an open laboratory extending until 21.1.2019. Report will be due 25.1.2019.

1. Characterize measurement equipment.

Measurement equipment:


For measurements the Electronic Explorer board is used:

Operation of Electronic Explorers

Set up:


Connect AWG 1 with SCOPE OSC1 DC to estimate the INL, DNL and signal to noise of the waveform generator and the oscilloscope.

Details:
Start the oscilloscope and the arbitrary waveform generator.
Select a sine signal with a frequency of 53.71749481 kHz an amplitude of 2 V and an offset of 2 V.
For channel 1 select a time range of 2 µs per division, range of 500 mV/div and offset of -2 V.
Creat a math function generating positive integer values: round(C1 * 2* 1024 + 200).
Check with the vertical minimum function of M1 that all values are positive.
Display only the positive integer values. Export the values. Source: Main Time, Type: Comma Separated Values, Untick Save Options Comments, Header and Label. Copy the integer data to the clipboard.
Copy the integer values into the input field of the FFT, INL, DNL tool:
FFT_Javascript_2017_Calibration.html
Do 'Read positive integer data'.
Set the number of points to 8192 and the number of bits to 12.
Do 'Generate Charts'.
Check the input signal for number of periods and range.

What is the signal to noise, INL and DNL value.
What is the maximum number of bits, which can be measured?
Discuss your results, document your challenges and results.
Make screenshots of the FFT analysis.

2. Measure static and dynamic performance of a C2C-DAC.


Build a 10-Bit C2C DAC according to the circuit below using only the operational amplifier LM324, not yet the sample and hold LF398 and connect it with the Electronic Explorer.

Details:
Data inputs and switches are realized with DIGITAL1 0..7 and DIGITAL2 8,9. DIGITAL3,4 22-31 will be later used as oscilloscope trigger signal.
DIGITAL2 12 will be later used for the sample and hold CLK.
AWG1 is connected as Voffset to shift the output to positive values.
SCOPE: OSC1 trigger DIGITAL2 9 or later Digital4 31.
SCOPE: OSC2 vint.
SCOPE: OSC3 vout.
SCOPE: OSC4 for monitoring other nodes and later Vout1.
VP+ = 4 V is used as positive voltage for the opamp.
VP- = -4 V is used as negative voltage for the opamp.
All GND pins (Bold dash or small white arrow on colored background) are connected on the Electronic Explorer.


Operational amplifier LM324:
 Sample and hold LF398:

Make a photo of your setup connected to the electronic explorer.
Start Waveforms.
Start the oscilloscope: Scope
Start the digital Patterns
Select DI0..DI10 as bus and counter.
Select voltage to control VP+ and VP-.

Ramp and sine measurement of the DAC:


Generate a binary counter pattern with the pattern generator and look with the oscilloscope at the output of the 10-bit DAC.


  1. Measure the capacitance value of each capacitance with a multi meter.

    Name C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
    C [pF]
    Name C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24
    C [pF]
    Name C25 C26 C27 C28 C29 C30 C31
    C [pF]

  2. What is the offset, maximum voltage, LSB and settling time of the DAC?
    Measure the signal Vint (after the DAC and before the opamp) and Vout (after the opamp).

    Details:
    Open the 'Patterns' window.
    Create a bus with D[0]..D[9].
    Use the type binary counter, output PP.
    Select a frequency of 10 MHz, 1 MHz, 100 kHz, 10 kHz under 'parameter' for the counter.
    Connect the MSB to OSC 1 DC as a trigger signal.
    Connect the output of the DAC to OSC2 DC and change the counter frequency until you have a sawtooth curve.
    Make sure that the settling time of the signal is ok for a full level transition.
    Use the full vertical range of the oscilloscope to minimize error.
    Channel 1 should show D9, channel 2 and 3 should show the output voltage before and after the opamp.

    measure the settling time using a '00..0', '11..1' pattern:

    Details:
    Open the 'Patterns' window.
    Select clock for the bus with values of 0 and 1023.
    Vary the clock frequency.
    Select clock for the bus with values of 511 and 512.
    Vary the clock frequency.

    Measure the settling time and switching noise of Vint and Vout.

    Document challenges, effort and results and discuss your results.

  3. Measure and extract INL and DNL using ReadOsci.html

    Details:
    With the oscilloscope do export data.
    Copy the data into the 'input data' field.
    Make sure to measure a positive ramp.
    Set 'DNL, INL start', 'DNL, INL averaging length', 'DNL, INL step' and 'DNL, INL number of values' to appropriate values.
    Set option for measurement analysis to 'Ramp INL, DNL'.
    Do 'Process oscilloscope data'.
    Document and discuss the result.
    Select a frequency of 10 MHz, 1 MHz, 100 kHz, 10 kHz under 'parameter' for the counter.

    What is the best frequency for the pattern generator for operation?
    Document challenges, effort and results and discuss your results.

  4. Select the best frequency from the previous task.
    Can you improve the INL and DNL of the transfer characteristic by changing capacitors?
    Measure the improved circuit.
    Document the improved capacitance values.
    Document challenges, effort and results and discuss your results.

  5. Use a digital sine input and measure signal to noise ratio using a fft.
    Import 10Bit_Sine43Periods.csv into the pattern generator of the Electronic Explorer.

    Details generating a sine signal:
    New calibrated ramp data is loaded into the digital pattern generator with Type: Custom, Output: PP, Edit: Parameters, Import file, open file, Browse, Ok, Import.

    Import 10Bit_Sine1Period.csv into the pattern generator of the Electronic Explorer.
    You can use DDS_Sim_Javascript_2016.html to generate other digital sine signals.
    Measure with different signal frequencies and analyze data with FFT_Javascript_2017_Calibration.html .

    Document challenges, effort and results and discuss your results.

  6. Use ReadOsci.html to calculate a calibration lookup table and generate a better ramp DDS_Sim_Javascript_2016.html and sine signal.

    Details, Step by Step:

    1) Start with DDS Javascript and fill 0..1023 into Calibration and do 'Ramp EE vector with calibration'
    2) Save the generated vectors on the drive and import them into the digital pattern generator:
    type custom, edit parameters, Import file, open file, browse ok import
    3) Measure the ramp with the oscilloscope and export the data
    4) Do ReadOsci.html
    and do 'Digital calibrated INL, DNL'
    The calibration data appear at the bottom
    5) Copy the calibration data into the DDS Javascript Calibration data and generate 1024 vectors.
    6) Use this vectors for the pattern generator.
    7) Look at the oscilloscope data with Read osci and the reduced number of codes and look for INL and DNL
    8) Use a sine waveform with calibration data and without, and compare SNR


    Can you improve the INL and DNL of the transfer ramp characteristic by using digital calibration?
    Can you improve the INL, DNL and signal to noise ratio of the sine characteristic by using digital calibration?
    Measure the improved circuit.
    Document challenges, effort and results and discuss your results.

  7. Document your results.

3. Operation with sample and hold


Connect the additional sample and hold circuit LF398 to the circuit.
Expand the bus to DIO0..DIO10 to include a trigger signal.
The imported waveforms will have always normal data followed by inverted data.
The length of the imported data can be 1024. This gives 512 values available for data output and analysis.
The sample and hold makes sure only normal data is sampled and present at Vout1 (OSC4).
Create a digital signal DIO12 for sample and hold clk control.
DIO12: Double frequency of bus, 30% duty cycle, 18 deg phase shift.

  1. Use a mid value to measure spikes at the output generated by the clk of the sample and hold.
    Import 10Bit_MidInv.csv into the pattern generator of the Electronic Explorer.
    Measure with different frequencies.
    What can you do limit the spikes?
    Document challenges, effort and results and discuss your results.

  2. Use a ramp input and measure INL, DNL.
    Import 10Bit_UpDnInv.csv into the pattern generator of the Electronic Explorer.
    Measure with different frequencies.
    Document challenges, effort and results and discuss your results.

  3. Use a digital sine input and measure signal to noise ratio using a fft.
    Import 10Bit_Sine43Inv.csv into the pattern generator of the Electronic Explorer.
    Import 10Bit_Sine1Inv.csv into the pattern generator of the Electronic Explorer.
    You can use DDS_Sim_Javascript_2016.html to generate other digital sine signals.
    Measure with different frequencies.
    Document challenges, effort and results and discuss your results.


4. Improvements


Suggest improvements for the instructions, the DAC circuit, the opamps and the sample and holds.

Report


Make a report with word or as a web page. You can use the source code of this web page or there is a web page template available here.
Additional files are here as an zip file (39 MB).

Send a pdf file of your report or zipped group directory with your data containing also a printout of the webpage in a pdf file to joerg.vollrath@hs-kempten.de.

You can use the freeware program PDF Creator for generating the pdf file.

Web report option



The directory should be named with the year, group number and last name

<year>_Group<###>_<Last_name>
Example: 2018_Group01_Vollrath

In this directory put the html and pdf file.
The file name should contain the date, the laboratory and your last names.

<year>_<month>_<Date>_InEl_Lab02_<Last_name1>_<Last_Name2>.pdf
Example: 2018_10_24_InEl_Lab04_Vollrath_studentx.html
Example: 2018_10_24_InEl_Lab04_Vollrath_studentx.pdf



Grading:

Each question should be answered. The answer should be correct/make sense. The submission date will be graded. Submission should happen until 28.1.2019. Late submission will be downgraded. A nice document format and correct use of English language and spelling is graded.